Renesas R5F104GEANA#V0
- Part No.:
- R5F104GEANA#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
R5F104GEANA#V0.pdf
- Description:
- IC MCU 16BIT 64KB FLASH 48HWQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,892
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F104GEANA#V0 from Renesas is a 48-pin LFQFP-packaged 16-bit RL78/G14 microcontroller with 48 KB flash, 5.5 KB RAM, and 4 KB data flash, operating at 1.6–5.5 V and delivering 44 DMIPS at 32 MHz for low-power industrial control applications including motor drive supervision and sensor-based HVAC monitoring.
For engineers reviewing the R5F104GEANA#V0 datasheet, R5F104GEANA#V0 pinout, R5F104GEANA#V0 application, or R5F104GEANA#V0 equivalent, key selection criteria include its 48-pin LFQFP (7 × 7 mm, 0.5 mm pitch) package, -40 to +85°C industrial temperature grade (D), integrated RTC with calendar support, 10-bit 20-channel ADC, and dual UART/LIN interfaces for embedded communication subsystems.
Technical Context
The R5F104GEANA#V0 implements the RL78 CPU core with CISC architecture, 3-stage pipeline, and configurable instruction timing (0.03125 µs @ 32 MHz to 30.5 µs @ 32.768 kHz). It integrates a Data Transfer Controller (DTC) supporting chain transfer and background operation during data flash rewriting.
Peripheral integration includes Timer Array Unit (TAU) with up to 8 channels, Real-time Clock with alarm/calendar functions, and Event Link Controller (ELC) enabling hardware-triggered peripheral linking without CPU intervention - critical for deterministic real-time response in safety-aware systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline and multiply/divide/accumulate instructions |
| Max Clock Speed | 32 MHz (44 DMIPS); high-speed on-chip oscillator selectable from 1–64 MHz with ±1.0% accuracy |
| Memory | 48 KB code flash (1 KB block size), 4 KB data flash (1M rewrite cycles), 5.5 KB RAM |
| Power Consumption | 66 μA/MHz active; 0.60 μA in STOP mode with RTC + LVD enabled |
| Analog Peripherals | 10-bit 20-channel ADC (VDD-referenced, internal 1.45 V ref & temp sensor), two 8-bit DAC outputs |
| Serial Interfaces | 3 UART/LIN channels, 4–10 I²C/simplified I²C channels, 3–8 CSI (SPI-compatible) channels |
| Timers | 8–12 × 16-bit timers (TAU, RJ, RD, RG), 1 × 12-bit interval timer, 1 × RTC with calendar/alarm |
Pinout & Package
Package: 48-pin LFQFP (7 × 7 mm, 0.5 mm pitch), RoHS-compliant, industrial-grade (−40 to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P10–P15 | CSI/I²C/UART/SCL/SDA/SO/SI pins | Configurable serial interface I/O supporting simultaneous SPI, I²C, and UART protocols |
| P16/P17 | TxD0/RxD0/INTP5/INTP4 | Dual-function UART channel with interrupt-capable timer input/output for protocol timing control |
| P20–P27 | ANI0–ANI7, AVREFP/AVREFM | 8-channel analog input bank with dedicated reference voltage inputs for precision ADC measurements |
| P30/P31 | RTC1HZ/SCK00/INTP3/TO03/TI03 | Real-time clock output and timer-capture inputs enabling time-stamped event logging and PWM synchronization |
| P50/P51 | RxD0/TxD0/INTP1/INTP2/TRGIOA/TRGIOB | On-chip debug interface pins supporting Renesas E2 emulator connection and trace-enabled debugging |
| P121/P122 | X1/X2/EXCLK | Crystal oscillator inputs supporting external 32.768 kHz RTC crystal or high-frequency main clock source |
| RESET/REGC/VDD/VSS | Reset, regulator capacitor, power rails | Hardware reset with brown-out detection; REGC requires 0.47–1 µF capacitor to VSS for stable internal regulator operation |
Key Features
| Feature | Design Value |
|---|---|
| SNOOZE mode operation | Enables peripheral-triggered wake-up while CPU remains halted - reduces average system power by >90% in polling-based sensor systems |
| Data Flash BGO | Background operation allows full program execution from flash memory during 4 KB data flash erase/write - eliminates latency in firmware-over-the-air updates |
| Event Link Controller (ELC) | Hardware routing of 19–26 event signals (e.g., ADC end-of-conversion, timer overflow) directly to peripherals - removes CPU ISR overhead for time-critical tasks |
| On-chip voltage detector (LVD) | 14-level programmable reset/interrupt threshold supports robust brown-out recovery across varying supply conditions in battery-powered equipment |
| Dual UART with LIN support | Full LIN 2.2 compliance (including sync-break detection and checksum) enables direct integration into automotive body electronics networks without external transceivers |
Applications
| Motor Control Supervision | HVAC Sensor Node |
|---|---|
|
Use Scenario: Monitoring current, temperature, and position feedback in BLDC motor drives for industrial pumps. IC Role / Device Role / Timing Role: Central controller executing commutation logic, ADC sampling at 100 kSPS, and PWM generation via TAU timers with sub-µs jitter. Use Value: Integrated 10-bit ADC with internal reference and 16-bit timers eliminate external signal conditioning and timing ICs - reducing BOM count by 3 components. |
Use Scenario: Wireless thermostat node collecting ambient temperature, humidity, and CO₂ via I²C sensors and transmitting via UART-to-LoRa bridge. IC Role / Device Role / Timing Role: Low-power host MCU managing sensor polling, RTC-based wake scheduling, and UART packet framing for sub-10 µA sleep current. Use Value: 0.60 µA STOP mode with RTC + LVD enables multi-year battery life using CR2032 cells in maintenance-free deployments. |
| Industrial PLC I/O Module | Smart Power Outlet |
|
Use Scenario: DIN-rail mounted digital I/O expansion module with opto-isolated inputs and relay drivers. IC Role / Device Role / Timing Role: Interface controller handling GPIO scanning, UART command parsing, and watchdog supervision of fieldbus communication. Use Value: 92 GPIO (configurable pull-up, open-drain, TTL) and 4 UART channels support mixed legacy RS-485 and modern Modbus TCP gateway functions in single-chip design. |
Use Scenario: Energy-monitoring smart outlet with current sensing, zero-cross detection, and Wi-Fi co-processor interface. IC Role / Device Role / Timing Role: Real-time energy calculation engine using ADC oversampling, zero-cross interrupt timing, and secure firmware update via data flash BGO. Use Value: Background data flash rewriting enables seamless OTA updates without interrupting power metering - meeting IEC 62056-21 compliance requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104GDANA#V0 | Same 48-pin LFQFP package, 32 KB flash, 4 KB RAM, identical peripheral set and pinout | Lower memory capacity suits simpler control loops without data logging or complex UI stacks | Select when firmware footprint remains under 28 KB and no future feature expansion is planned |
| R5F104GEAFP#V0 | Same flash/RAM specs but 44-pin LQFP (10 × 10 mm, 0.8 mm pitch) package with reduced I/O count (68 vs. 92) | Targeted at space-constrained designs where fewer analog inputs or serial interfaces are required | Choose for cost-sensitive consumer products where PCB area savings outweigh I/O flexibility needs |
Compared with R5F104GDANA#V0, the R5F104GEANA#V0 provides 16 KB additional flash for firmware resilience and data buffering; versus R5F104GEAFP#V0, it delivers 24 more GPIO and two extra UART channels - enabling full-featured industrial gateways without external bus expanders.
Availability
R5F104GEANA#V0 is available at Aetrix Electronics and suitable for industrial motor control, HVAC sensor nodes, PLC I/O modules, and smart power outlets requiring stable component supply across extended product lifecycles.
Supply support for R5F104GEANA#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power management solutions for industrial, automotive, and IoT markets.
The RL78/G14 family targets cost-sensitive, ultra-low-power general-purpose applications - balancing performance, integration, and energy efficiency for battery-operated and mains-powered embedded systems.
FAQ
What is the operating temperature range for R5F104GEANA#V0?
The R5F104GEANA#V0 is rated for industrial operation from −40°C to +85°C (D-grade), validated per JEDEC JESD22-A108 and qualified for continuous use in enclosed control cabinets and outdoor-rated enclosures with passive thermal management.
Does R5F104GEANA#V0 support in-circuit debugging?
Yes, R5F104GEANA#V0 supports full on-chip debugging via its dedicated SWD interface using pins P50 (TRGIOA) and P51 (TRGIOB), compatible with Renesas E2/E2 Lite emulators and third-party tools adhering to ARM Serial Wire Debug specification.
How many UART channels does R5F104GEANA#V0 include?
R5F104GEANA#V0 integrates three UART channels, all supporting LIN 2.2 protocol features including automatic sync-break detection, checksum generation, and slave node response timing - confirmed in Section 22.3 of R01DS0053EJ0370.
What is the maximum ADC sampling rate for R5F104GEANA#V0?
The R5F104GEANA#V0 ADC achieves up to 100 kSPS at 10-bit resolution when using the high-speed sampling mode and internal clock source, with conversion time of 10 µs per sample - sufficient for closed-loop motor current sensing at 10 kHz update rates.
Can R5F104GEANA#V0 operate from a single 3.3 V supply?
Yes, R5F104GEANA#V0 operates across 1.6–5.5 V, making 3.3 V a fully supported and commonly used supply voltage; all I/Os are 5 V-tolerant when configured as inputs, simplifying interface with legacy 5 V peripherals.
R5F104GEANA#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-WFQFN Exposed Pad
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 34
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 5.5K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 10x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104GEANA#V0 FAQ
1.How can I place an order for R5F104GEANA#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104GEANA#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104GEANA#V0 reliable?
The price and inventory of R5F104GEANA#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104GEANA#V0 is usually 5 days.
3.What payment methods are accepted for R5F104GEANA#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104GEANA#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104GEANA#V0?
R5F104GEANA#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104GEANA#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104GEANA#V0?
For technical support, including R5F104GEANA#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104GEANA#V0 requirements.
6.How does Aetrix verify that R5F104GEANA#V0 is sourced from the original manufacturer or authorized distributors?
All R5F104GEANA#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104GEANA#V0 meets industry standards.
7.What is the process for return or replacement of R5F104GEANA#V0?
All R5F104GEANA#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104GEANA#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104GEANA#V0 part is unused and in its original packaging.
Return procedure for R5F104GEANA#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F104GEANA#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

