Renesas R5F104GJAFB#X0
- Part No.:
- R5F104GJAFB#X0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
R5F104GJAFB#X0.pdf
- Description:
- IC MCU 16BIT 256KB FLASH 48LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F104GJAFB#X0 from Renesas is a 48-pin LFQFP, 0.5 mm pitch, industrial-grade (−40°C to +105°C) RL78/G14 16-bit MCU with 192 KB flash, 20 KB RAM, and 8 KB data flash. It delivers 44 DMIPS at 32 MHz, operates from 1.6 V to 5.5 V, and supports ultra-low-power modes including 0.60 μA STOP mode with RTC and LVD active - used in battery-powered industrial sensors and smart metering endpoints.
For engineers reviewing the R5F104GJAFB#X0 datasheet, R5F104GJAFB#X0 pinout, R5F104GJAFB#X0 application, or R5F104GJAFB#X0 equivalent, key selection criteria include its integrated 10-bit 20-channel ADC, dual UART/LIN support, real-time clock with calendar, and hardware DTC/ELC for deterministic low-power peripheral coordination.
Technical Context
The R5F104GJAFB#X0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz) to 30.5 μs (32.768 kHz). It integrates a 12-bit interval timer, RTC with alarm/calendar, and watchdog timer with dedicated low-speed oscillator.
Peripheral subsystems include 8–12 channels of 16-bit timers (TAU, RJ, RD, RG), up to 10-channel I²C/Simplified I²C, 3–4 UART/LIN channels, 3–8 CSI channels, and an 8-bit DAC with real-time output capability - all configurable via Event Link Controller (ELC) for interrupt-free event chaining.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline and multiply/divide/accumulate instructions |
| Max Clock Speed | 32 MHz (44 DMIPS); high-accuracy on-chip oscillator ±1.0% over −40°C to +85°C |
| Memory | 192 KB code flash (1 KB blocks), 20 KB RAM, 8 KB data flash with 1M rewrite cycles and background operation |
| Power Modes | HALT (66 μA/MHz), STOP (0.60 μA with RTC+LVD), SNOOZE - enables multi-year battery life in sensing nodes |
| Analog Peripherals | 10-bit 20-channel ADC (VDD-referenced, internal 1.45 V ref, temp sensor), 8-bit dual DAC (0–VDD output) |
| Serial Interfaces | 3 UART/LIN, 4–10 I²C/Simplified I²C, 3–8 CSI (SPI-compatible), 1 SSI channel |
| Timers & RTC | 8–12 × 16-bit timers, 12-bit interval timer, calendar RTC (99-year range, alarm, correction), watchdog timer |
Pinout & Package
Package: 48-pin LFQFP, 7 mm × 7 mm, 0.5 mm pitch, industrial temperature grade (−40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00/P01 | TxD1/RxD1, TI00/TO00 | Full-duplex UART1 with timer capture/compare; supports asynchronous communication and pulse timing |
| P10–P17 | SPI/I²C/UART peripherals (SCK11, SI11, SO11, SCL11, etc.) | Multiplexed serial interface pins configurable via PIOR registers; enable concurrent SPI master/slave and I²C bus control |
| P20–P27 | ANI0–ANI7, AVREFP/AVREFM, ANO0/ANO1 | 8 analog input channels with differential reference support; two analog outputs for DAC feedback or actuator control |
| P30/P31 | INTP3/RTC1HZ, INTP4/TI03/TO03 | Dedicated RTC 1 Hz output and general-purpose timer I/O for time-triggered control and wake-up events |
| P50/P51 | RxD0/TxD0, INTP1/INTP2 | UART0 with hardware flow control and interrupt-capable GPIO; used for debug interface (TOOLRxD/TOOLTxD) |
| P121/P122 | X1/X2 crystal inputs | Supports 32.768 kHz crystal for RTC accuracy or external 1–20 MHz clock source for main system timing |
| RESET, REGC, VDD, VSS | Reset control, regulator capacitor, power rails | REGC requires 0.47–1 μF capacitor to VSS; RESET is active-low with internal pull-up; VDD/VSS support 1.6–5.5 V operation |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-power STOP mode | 0.60 μA with RTC and LVD active - enables decade-scale battery operation in remote monitoring devices |
| Data Flash BGO | Background operation allows full CPU execution during 8 KB data flash rewrites - no firmware stalls during field updates |
| Event Link Controller (ELC) | Links 19–26 peripheral events without CPU intervention - reduces latency and ISR overhead in real-time control loops |
| Hardware DTC | Configurable DMA-like transfers triggered by interrupts or peripherals - offloads CPU for sensor data acquisition and buffer management |
| On-chip debug & self-programming | Boot swap and flash shield window functions enable secure firmware updates and field recovery without external programmer |
Applications
| Industrial Sensor Node | Smart Energy Meter |
|---|---|
Use Scenario: Battery-powered temperature/humidity/pressure sensor collecting data every 15 minutes and transmitting via UART-to-LoRaWAN gateway. IC Role / Device Role / Timing Role: Main controller executing sensor readout, RTC-based scheduling, low-power state management, and UART framing. Use Value: 0.60 μA STOP mode extends 2×AA battery life beyond 10 years; 10-bit ADC ensures ±0.5°C thermal measurement accuracy. | Use Scenario: DIN-rail mounted electricity meter performing real-time voltage/current sampling, tariff calculation, and RS-485 communication. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC interface, RTC calendar for billing periods, LIN/UART for HAN communication, and tamper detection. Use Value: Integrated 20-channel ADC with internal reference eliminates external precision references; data flash BGO enables seamless firmware upgrades during meter operation. |
| Home Appliance Control | Factory Automation I/O Module |
Use Scenario: Washing machine main board controlling motor drivers, water valves, display, and user interface buttons. IC Role / Device Role / Timing Role: Real-time motor timing (TAU), keypad scan (KR0–KR7), buzzer output (PCLBUZ0/1), and LIN bus communication with display panel. Use Value: On-chip PCLBUZ controllers drive piezo elements directly; ELC synchronizes valve actuation with motor phase signals without CPU polling. | Use Scenario: DIN-rail PLC I/O expansion module acquiring 16 digital inputs and 8 analog inputs, then reporting via Modbus RTU over RS-485. IC Role / Device Role / Timing Role: Peripheral coordinator using DTC for burst ADC reads, UART for Modbus framing, and GPIO for isolation driver control. Use Value: Hardware DTC moves 16-sample ADC buffers into RAM without CPU cycles; 48-pin LFQFP provides sufficient GPIO for discrete I/O routing and diagnostics LEDs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104GHAFB#X0 | Same 48-pin LFQFP package, 128 KB flash, 16 KB RAM, identical peripheral set and power specs | Lower memory footprint suits simpler control tasks without data logging or complex UI | Select when firmware size < 128 KB and cost sensitivity outweighs future scalability needs |
| R5F104GKAFB#X0 | Same 48-pin LFQFP package, 256 KB flash, 24 KB RAM, otherwise identical architecture and peripherals | Higher memory headroom supports OTA updates, encryption stacks, or richer HMI features | Select when firmware growth projection exceeds 192 KB or dual-bank flash security is required |
Compared with R5F104GHAFB#X0 and R5F104GKAFB#X0, the R5F104GJAFB#X0 offers optimal balance of memory (192 KB flash/20 KB RAM), industrial temperature rating, and low-power performance - making it ideal for mid-complexity edge nodes where scalability and battery life are both critical.
Availability
R5F104GJAFB#X0 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart energy meters, and home appliance control systems requiring stable component supply across extended product lifecycles.
Supply support for R5F104GJAFB#X0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive, battery-operated, and industrial control applications - combining ultra-low active and standby current with rich analog and communication peripherals.
FAQ
What is the operating temperature range for the R5F104GJAFB#X0?
The R5F104GJAFB#X0 is rated for industrial operation from −40°C to +105°C, as indicated by the 'G' suffix in the part number. This makes it suitable for deployment in harsh environments such as factory floors, outdoor utility meters, and automotive under-hood modules where extended thermal stability is required. The device maintains full functionality and parameter compliance across this full range.
Does the R5F104GJAFB#X0 support in-circuit debugging without external tools?
Yes, the R5F104GJAFB#X0 includes an on-chip debug interface accessible via the P50 (TOOLRxD) and P51 (TOOLTxD) pins. It supports full break-point debugging, register inspection, and flash programming through Renesas' E2 studio and CS+ IDEs using standard SWD or UART-based debug adapters - eliminating need for external JTAG emulators in most development workflows.
How many UART/LIN interfaces does the R5F104GJAFB#X0 provide?
The R5F104GJAFB#X0 provides three UART channels, all with LIN bus protocol support. These are implemented on P00/P01 (UART1), P13/P14 (UART2), and P50/P51 (UART0). Each channel supports automatic LIN header detection, checksum generation, and slave node response handling - enabling direct integration into automotive body control or industrial sub-networks without external transceivers.
Can the R5F104GJAFB#X0 execute code while rewriting data flash memory?
Yes, the R5F104GJAFB#X0 supports Background Operation (BGO) for its 8 KB data flash memory. During a data flash write or erase operation, the CPU can continue executing instructions from code flash - enabling uninterrupted real-time processing, communication, or sensor sampling. This capability is essential for fail-safe firmware updates and runtime parameter storage in mission-critical systems.
What packaging and lead finish does the R5F104GJAFB#X0 use?
The R5F104GJAFB#X0 uses a 48-pin LFQFP package (7 mm × 7 mm, 0.5 mm pitch) with lead-free (Pb-free) matte tin finish, compliant with JEDEC J-STD-020 moisture sensitivity level 3. The '#X0' suffix indicates embossed tape packaging per JEDEC standard, suitable for automated SMT placement. The package includes exposed thermal pad design for enhanced thermal dissipation in high-duty-cycle applications.
R5F104GJAFB#X0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-LQFP
- Series:
- RL78/G14
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 34
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 24K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 10x8/10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104GJAFB#X0 FAQ
1.How can I place an order for R5F104GJAFB#X0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104GJAFB#X0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104GJAFB#X0 reliable?
The price and inventory of R5F104GJAFB#X0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104GJAFB#X0 is usually 5 days.
3.What payment methods are accepted for R5F104GJAFB#X0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104GJAFB#X0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104GJAFB#X0?
R5F104GJAFB#X0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104GJAFB#X0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104GJAFB#X0?
For technical support, including R5F104GJAFB#X0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104GJAFB#X0 requirements.
6.How does Aetrix verify that R5F104GJAFB#X0 is sourced from the original manufacturer or authorized distributors?
All R5F104GJAFB#X0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104GJAFB#X0 meets industry standards.
7.What is the process for return or replacement of R5F104GJAFB#X0?
All R5F104GJAFB#X0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104GJAFB#X0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104GJAFB#X0 part is unused and in its original packaging.
Return procedure for R5F104GJAFB#X0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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