Renesas R5F104GJANA#20
- Part No.:
- R5F104GJANA#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
R5F104GJANA#20.pdf
- Description:
- IC MCU 16BIT 256KB FLASH 48HWQFN
- Quantity:
- Payment:

- Shipping:

Inventory:675
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Product details
Overview
R5F104GJANA#20 from Renesas is a 48-pin HWQFN-packaged RL78/G14 16-bit microcontroller with 192 KB flash, 8 KB data flash, and 20 KB RAM, operating from 1.6–5.5 V at -40 to +105°C (industrial G-grade), delivering 44 DMIPS at 32 MHz for low-power embedded control in motor drives, sensor nodes, and industrial HMI.
For engineers reviewing the R5F104GJANA#20 datasheet, R5F104GJANA#20 pinout, R5F104GJANA#20 application, or R5F104GJANA#20 equivalent, key selection considerations include its 48-pin HWQFN-0.5 mm pitch package, integrated RTC + LVD + BGO-capable data flash, and support for UART/LIN, I²C, and CSI interfaces in thermally demanding environments.
Technical Context
The R5F104GJANA#20 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 µs (32 MHz) to 30.5 µs (32.768 kHz), plus multiply/divide/accumulate instructions and 1 MB address space. It integrates a high-accuracy ±1.0% on-chip oscillator (1–64 MHz selectable) and dual-clock domain operation for concurrent system and subsystem timing.
Its peripheral set includes 12-channel 16-bit Timer Array Unit (TAU), 1-channel real-time clock with calendar/alarm/correction, 10-bit 20-channel ADC with internal 1.45 V reference and temperature sensor, and Event Link Controller (ELC) enabling hardware-triggered peripheral chaining without CPU intervention - critical for deterministic low-latency control loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC with 3-stage pipeline, 1 MB address space, 44 DMIPS @ 32 MHz |
| Memory | 192 KB code flash (1 KB blocks), 8 KB data flash (1M rewrite cycles), 20 KB SRAM |
| Operating Voltage & Temp | 1.6–5.5 V supply; -40 to +105°C ambient (G-grade industrial) |
| Power Consumption | 66 μA/MHz active; 0.60 μA in STOP mode (RTC + LVD only) |
| Analog Peripherals | 10-bit 20-channel ADC with internal 1.45 V ref and temp sensor; two 8-bit DAC outputs |
| Serial Interfaces | Up to 8 CSI channels, 4 UART/LIN channels, 10 I²C/simplified I²C channels |
| Timers & Clock | 12× 16-bit TAU timers, 1× RTC (99-year calendar), 1× watchdog, ±1.0% on-chip oscillator (1–64 MHz) |
Pinout & Package
Package: 48-pin HWQFN (7 × 7 mm, 0.5 mm pitch), exposed die pad recommended to be connected to VSS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00 | TxD1 / TI00 / TRGCLKA | Primary UART transmit; timer input; debug clock input; supports 1.8/2.5/3 V level shifting |
| P01 | RxD1 / TO00 / TRGCLKB | Primary UART receive; timer output; debug clock output; TTL-compatible input buffer |
| P10–P17 | CSI/I²C/UART/SPI peripherals | Multi-function pins supporting CSI (SPI-like), I²C, UART, and TRDIO (touch/segment driver) with programmable redirection |
| P20–P27 | ADC inputs / AVREFP / AVREFM | 20-channel analog input group with dedicated 1.45 V internal reference and differential voltage sensing capability |
| P30–P31 | INTP3 / RTC1HZ / TI03 / TO03 | Real-time clock interrupt output (1 Hz); timer input/output; supports wake-up from STOP mode |
| P50–P51 | RxD0/TxD0 / SO00/SI00 / TOOLRxD/TOOLTxD | Dual-role UART/serial interface with on-chip debug tool communication path |
| P121–P122 | X1 / X2 / EXCLK | Crystal oscillator inputs (32.768 kHz or 1–20 MHz) or external clock source for precise timing |
| RESET / REGC / VDD / VSS | Power & reset control | Active-low reset with built-in POR; REGC requires 0.47–1 µF capacitor to VSS for regulator stability |
Key Features
| Feature | Design Value |
|---|---|
| SNOOZE mode operation | Enables background data flash rewriting (BGO) while CPU executes code from flash - no interrupt latency penalty |
| Event Link Controller (ELC) | Hardware-peripheral linking eliminates CPU polling/interrupt overhead for time-critical signal chains (e.g., ADC → DMA → UART) |
| On-chip debug & self-programming | Full on-chip debug via single-wire interface; boot swapping and flash shield window protect firmware integrity during updates |
| Dual-voltage I/O capability | I/O ports support 1.8/2.5/3 V logic interfacing without level shifters - simplifies mixed-voltage system design |
| Low-power RTC + LVD | Sub-μA real-time clock with calendar/alarm and configurable voltage detector (14 levels) enable fail-safe monitoring in battery-backed systems |
Applications
| Industrial Motor Control | Smart Sensor Node |
|---|---|
Use Scenario: Brushless DC motor commutation with current sensing and thermal monitoring in HVAC blowers. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, sampling 10-bit ADC at 100 kSPS, generating PWM via TAU timers with ELC-synchronized ADC triggers. Use Value: 66 μA/MHz active power and STOP-mode RTC wake-up reduce average system power by >40% vs. legacy 8-bit MCUs in intermittent duty cycles. |
Use Scenario: Battery-powered environmental sensor hub aggregating temperature, humidity, and CO₂ data for wireless transmission. IC Role / Device Role / Timing Role: System-on-chip managing sensor I²C reads, RTC-timed sampling, BGO data flash logging, and UART/LIN host interface. Use Value: 0.60 μA STOP mode with RTC + LVD enables >5-year battery life; internal 1.45 V ADC reference ensures stable readings across voltage decay. |
| Human-Machine Interface | Industrial PLC I/O Module |
Use Scenario: Touch-button and LED status panel for factory equipment with ESD-hardened front-end. IC Role / Device Role / Timing Role: Dedicated touch controller using TRDIO pins and on-chip comparator; drives buzzer and LEDs via PCLBUZ units and GPIO. Use Value: Integrated touch I/O and 8-bit DACs eliminate external drivers; N-ch open-drain I/O withstands 6 V transients per IEC 61000-4-2 Level 4. |
Use Scenario: DIN-rail mounted digital input module converting 24 V field signals to isolated CAN/LIN bus. IC Role / Device Role / Timing Role: Signal conditioner and protocol bridge: 24 V opto-isolated inputs → 10-bit ADC → UART-to-LIN translation with CRC and error recovery. Use Value: 1.6–5.5 V operation accommodates wide-input DC-DC rails; 14-level LVD detects brown-out before logic corruption in noisy plant-floor environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104GHANA#20 | 128 KB flash, 8 KB data flash, 16 KB RAM; same 48-pin HWQFN package and G-grade temp range | Lower memory footprint suits simpler control tasks (e.g., basic timer-based sequencers) | Select when application code size < 128 KB and cost sensitivity outweighs need for future firmware expansion headroom |
| R5F104GKANA#20 | 256 KB flash, 8 KB data flash, 24 KB RAM; identical package, pinout, and peripheral set | Supports larger RTOS deployments or complex communication stacks (e.g., Modbus TCP offload) | Choose for designs requiring >192 KB flash margin or planning multi-year feature upgrades without PCB revision |
Compared with R5F104GHANA#20 and R5F104GKANA#20, the R5F104GJANA#20 delivers optimal balance of memory (192 KB flash), real-time performance (44 DMIPS), and ultra-low power (0.60 μA STOP) in the 48-pin HWQFN industrial package - making it ideal for mid-complexity edge controllers where scalability and thermal robustness are co-prioritized.
Availability
R5F104GJANA#20 is available at Aetrix Electronics and suitable for industrial motor control, smart sensor nodes, human-machine interface panels, and PLC I/O modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for R5F104GJANA#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCU performance for general-purpose industrial and consumer applications, emphasizing energy efficiency, integrated analog, and robust debug/programming features.
FAQ
What is the maximum operating frequency and associated DMIPS rating for the R5F104GJANA#20?
The R5F104GJANA#20 operates at up to 32 MHz with a measured performance of 44 DMIPS. This rating reflects Dhrystone 2.1 benchmark execution under typical conditions with the RL78 CPU core's 3-stage pipeline and optimized instruction set - not a theoretical peak. The R5F104GJANA#20 achieves this while maintaining 66 μA/MHz active current consumption.
Does the R5F104GJANA#20 support background data flash rewriting (BGO) while executing application code?
Yes, the R5F104GJANA#20 supports background operation (BGO) for data flash rewriting. During BGO, the CPU can execute instructions from code flash memory while the data flash is being rewritten - enabling seamless firmware parameter updates or logging without halting real-time control tasks. This is enabled via the Flash Self-Programming Library and requires proper RAM allocation (start address F9F00H).
What is the industrial temperature grade and package type of the R5F104GJANA#20?
The R5F104GJANA#20 is rated for industrial operation from -40 to +105°C (G-grade) and housed in a 48-pin HWQFN package (7 × 7 mm, 0.5 mm pitch) with an exposed die pad. Its ordering suffix "NA" explicitly denotes the HWQFN package, and "G" in the part number sequence confirms the extended temperature qualification - validated per JEDEC JESD22-A108.
How many analog input channels and what ADC resolution does the R5F104GJANA#20 provide?
The R5F104GJANA#20 integrates a 10-bit successive-approximation ADC with up to 20 analog input channels (ANI0–ANI19). It includes an internal 1.45 V reference voltage and on-die temperature sensor, enabling accurate measurements across the full 1.6–5.5 V supply range without external references - critical for battery-operated or wide-input industrial sensors.
Is the R5F104GJANA#20 pin-compatible with other RL78/G14 variants in the same 48-pin HWQFN package?
Yes, the R5F104GJANA#20 shares identical pinout, electrical characteristics, and peripheral mapping with all other RL78/G14 devices in the 48-pin HWQFN package (e.g., R5F104GHANA#20, R5F104GKANA#20), including identical function assignment for P00–P27, P30–P31, P50–P51, and oscillator/reset pins - enabling drop-in memory-scaling substitutions without PCB changes.
R5F104GJANA#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-WFQFN Exposed Pad
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Last Time Buy
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 34
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 24K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 10x8/10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104GJANA#20 FAQ
1.How can I place an order for R5F104GJANA#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104GJANA#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104GJANA#20 reliable?
The price and inventory of R5F104GJANA#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104GJANA#20 is usually 5 days.
3.What payment methods are accepted for R5F104GJANA#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104GJANA#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104GJANA#20?
R5F104GJANA#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104GJANA#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104GJANA#20?
For technical support, including R5F104GJANA#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104GJANA#20 requirements.
6.How does Aetrix verify that R5F104GJANA#20 is sourced from the original manufacturer or authorized distributors?
All R5F104GJANA#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104GJANA#20 meets industry standards.
7.What is the process for return or replacement of R5F104GJANA#20?
All R5F104GJANA#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104GJANA#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104GJANA#20 part is unused and in its original packaging.
Return procedure for R5F104GJANA#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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