Renesas R5F104JDAFA#10
- Part No.:
- R5F104JDAFA#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 52-LQFP
- Datasheet:
-
R5F104JDAFA#10.pdf
- Description:
- IC MCU 16BIT 48KB FLASH 52LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,280
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Product details
Overview
R5F104JDAFA#10 from Renesas is a 52-pin LQFP-0.65 mm pitch, industrial-grade (D) 16-bit RL78/G14 microcontroller with 96 KB flash, 12 KB RAM, and 8 KB data flash. It delivers 44 DMIPS at 32 MHz, operates from 1.6–5.5 V, and supports ultra-low-power modes (66 μA/MHz active, 0.60 μA RTC+LVD). It targets battery-powered industrial sensor nodes requiring integrated analog peripherals and LIN-capable UART.
For engineers reviewing the R5F104JDAFA#10 datasheet, R5F104JDAFA#10 pinout, R5F104JDAFA#10 application, or R5F104JDAFA#10 equivalent, key selection criteria include its 52-pin LQFP package, 96 KB/12 KB/8 KB memory configuration, -40 to +85°C industrial temperature rating, and support for hardware-accelerated data transfer via DTC and event-driven peripheral control via ELC.
Technical Context
The R5F104JDAFA#10 implements the RL78 CPU core with CISC architecture, 3-stage pipeline, and configurable instruction timing (0.03125 µs @ 32 MHz to 30.5 µs @ 32.768 kHz). It integrates a 12-bit interval timer, real-time clock with calendar/alarm, and watchdog timer with dedicated low-speed oscillator.
Peripheral integration includes up to 20-channel 8/10-bit ADC with internal 1.45 V reference and temperature sensor, two 8-bit DAC channels, up to 12× 16-bit timers (TAU, RJ, RD, RG), 3–4 UART/LIN channels, 4–10 I²C interfaces, and 3–8 CSI (SPI-compatible) channels - all accessible through flexible I/O redirection registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline and multiply/divide instructions |
| Max Clock | 32 MHz (44 DMIPS); high-accuracy on-chip oscillator ±1.0% over -20 to +85°C |
| Memory | 96 KB code flash (1 KB blocks), 12 KB RAM, 8 KB data flash with 1M rewrite cycles |
| Power | 1.6–5.5 V supply; 66 μA/MHz active current; 0.60 μA in STOP mode with RTC + LVD |
| Analog | 20-channel 10-bit ADC (VDD-referenced), dual 8-bit DACs (0–VDD output), internal temp sensor & 1.45 V ref |
| Peripherals | 4 UART/LIN, 10 I²C, 8 CSI, 12× 16-bit timers, DTC, ELC, BCD correction, key interrupt, buzzer controller |
| Temp Range | -40°C to +85°C (industrial grade, 'D' suffix) |
Pinout & Package
Package: 52-pin LQFP, 10 × 10 mm body, 0.65 mm pitch, exposed pad not present (standard LQFP).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00 | TxD1 / TI00 / TRGCLKA | Primary UART1 transmit; timer input; trace clock A; multiplexed with debug TRJO0 |
| P01 | RxD1 / TO00 / TRGCLKB | Primary UART1 receive; timer output; trace clock B; multiplexed with debug TRJIO0 |
| P10–P17 | CSI1/SI11/SDA11/SO11/SCL11/TRDIOD1–TRDIOA0 | Dedicated serial interface group supporting SPI/I²C/UART-like protocols with flexible signal routing |
| P120 | VCOUT0 / ANI19 | Comparator output channel 0; 19th analog input channel - enables analog monitoring with digital output assertion |
| P121/P122 | X1 / X2 / EXCLK | Crystal oscillator inputs (32.768 kHz or higher) or external clock source for precise timing |
| P137 | INTP0 | Highest-priority external interrupt input, usable for wake-up or critical fault detection |
| P147 | VCOUT1 / ANI18 | Comparator output channel 1; 18th analog input - supports dual-threshold analog window detection |
| RESET | Active-low reset input | Asynchronous reset with internal pull-up; accepts external debounced reset or power-on-reset assertion |
| REGC | Voltage regulator bypass capacitor | Must connect 0.47–1 µF capacitor to VSS for stable internal LDO operation |
| VDD/VSS | Power supply pins | Single 1.6–5.5 V supply; multiple VDD/VSS pairs ensure noise immunity and low-impedance return paths |
Key Features
| Feature | Design Value |
|---|---|
| SNOOZE mode operation | Enables background data flash rewriting while CPU remains halted - reduces system latency during firmware updates |
| Data Transfer Controller (DTC) | Offloads CPU for memory-to-peripheral transfers (e.g., ADC → RAM), freeing core for real-time tasks |
| Event Link Controller (ELC) | Hardware-triggered peripheral chaining (e.g., ADC end-of-conversion → DMA trigger → timer start) without CPU intervention |
| On-chip debug & self-programming | Full on-chip debug via single-wire SWD; boot swapping and flash shield window enable secure field firmware updates |
| Integrated LIN physical layer support | UART peripherals include automatic sync-break detection and checksum generation per LIN 2.x spec - no external transceiver needed for basic node roles |
| Flexible I/O redirection | Peripheral functions (e.g., UART, CSI) can be reassigned to alternate pins via PIO register settings - simplifies PCB layout reuse |
Applications
| Industrial Sensor Node | Smart HVAC Actuator |
|---|---|
Use Scenario: Battery-powered temperature/humidity/pressure sensor collecting data every 10 seconds and transmitting via LIN bus to central controller. IC Role / Device Role / Timing Role: Main system controller executing sensor acquisition, calibration, LIN protocol stack, and ultra-low-power scheduling. Use Value: 0.60 μA STOP mode extends 2xAA battery life beyond 5 years; integrated 10-bit ADC and LIN-capable UART eliminate discrete signal conditioning and transceiver ICs. | Use Scenario: Motorized damper control module receiving setpoint commands over LIN and driving bidirectional DC motor with current feedback. IC Role / Device Role / Timing Role: Real-time actuator controller managing PWM generation, current sensing (via ADC), position feedback, and LIN communication. Use Value: 12× 16-bit timers support simultaneous motor PWM, encoder counting, and dead-time insertion; DTC automates ADC sampling → RAM buffering → PID calculation chain. |
| Programmable Logic Controller I/O Module | Energy Meter Front-End |
Use Scenario: DIN-rail mounted remote I/O module converting 4–20 mA analog inputs and dry-contact digital inputs into Modbus RTU over RS-485. IC Role / Device Role / Timing Role: Protocol gateway and signal conditioner interfacing field devices to backplane communication. Use Value: 20-channel ADC with internal reference ensures accurate current loop measurement; ELC links analog conversion completion to UART transmission trigger - deterministic latency under 5 µs. | Use Scenario: Residential smart meter measuring voltage/current/energy via shunt or CT sensors and reporting via PLC or RF mesh network. IC Role / Device Role / Timing Role: Metrology front-end processor handling analog acquisition, RMS calculation, tamper detection, and secure data logging. Use Value: Dual 8-bit DACs generate precision calibration references; 8 KB data flash stores 30 days of tamper-protected energy logs with 1M write endurance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104JEAFA#10 | Same 52-pin LQFP package, but 128 KB flash / 16 KB RAM / 8 KB data flash | Required when application firmware exceeds 96 KB or needs larger RAM for complex protocol stacks | Select if future firmware growth headroom or larger buffer requirements justify higher cost and memory overhead |
| R5F104JDGFA#10 | Same memory config (96 KB/12 KB/8 KB) but rated for -40 to +105°C (G grade) | Necessary for under-hood automotive or high-ambient industrial enclosures exceeding +85°C | Choose only when ambient operating temperature exceeds +85°C; otherwise R5F104JDAFA#10 offers better cost/performance balance |
Compared with R5F104JEAFA#10 and R5F104JDGFA#10, the R5F104JDAFA#10 provides optimal cost-efficiency for industrial sensor and actuator designs operating within -40°C to +85°C and requiring ≤96 KB code space - avoiding unnecessary flash/RAM overhead or extended temperature qualification costs.
Availability
R5F104JDAFA#10 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart HVAC actuators, programmable logic controller I/O modules, and energy meter front-ends requiring stable component supply across multi-year production cycles.
Supply support for R5F104JDAFA#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive industrial and consumer applications requiring robust analog integration, LIN/UART/I²C connectivity, and long battery life - without sacrificing performance or debug capability.
FAQ
What is the maximum operating frequency and corresponding performance of the R5F104JDAFA#10?
The R5F104JDAFA#10 operates at up to 32 MHz with a peak performance of 44 DMIPS. Its high-accuracy on-chip oscillator maintains ±1.0% frequency stability across 1.8–5.5 V supply and -20 to +85°C ambient, eliminating need for external crystal in many timing-tolerant applications. This allows the R5F104JDAFA#10 to drive real-time control loops and communication stacks without external timing components.
Does the R5F104JDAFA#10 support LIN bus communication, and how is it implemented?
Yes, the R5F104JDAFA#10 supports LIN 2.x protocol natively through its UART peripherals, which include hardware sync-break detection, checksum generation, and identifier filtering. No external LIN transceiver is required for basic slave-node functionality. The R5F104JDAFA#10's UART modules can be configured for LIN mode via control registers, enabling direct connection to LIN bus wiring with only passive termination resistors.
What are the memory resources allocated to the R5F104JDAFA#10, and how is data flash endurance specified?
The R5F104JDAFA#10 integrates 96 KB of code flash memory (organized in 1 KB blocks), 12 KB of on-chip RAM, and 8 KB of data flash memory. Data flash supports background operation (BGO) and guarantees 1,000,000 write/erase cycles (typical) at VDD = 1.8–5.5 V - sufficient for daily firmware update logging or decade-long energy meter data retention. The R5F104JDAFA#10 also supports flash shield window and block erase prohibition for security-critical applications.
How does the R5F104JDAFA#10 achieve ultra-low power consumption, and what are the lowest current modes?
The R5F104JDAFA#10 achieves ultra-low power via multiple hardware-controlled sleep modes: HALT (CPU stopped, peripherals active), STOP (all clocks halted except RTC/LVD), and SNOOZE (selected peripherals active while CPU sleeps). In STOP mode with only RTC and LVD enabled, it draws just 0.60 μA at 25°C - verified per datasheet R01DS0053EJ0370. This enables multi-year battery life in intermittent-sensing applications, and the R5F104JDAFA#10 retains full SRAM content and register state across all low-power modes.
What debug and programming interfaces are supported by the R5F104JDAFA#10?
The R5F104JDAFA#10 supports single-wire debug (SWD) via the TOOL0 pin (P40) and TRJIO0/TRJO0 pins (P01/P00), enabling full JTAG-equivalent debugging including breakpoints, watchpoints, and real-time memory inspection. It also supports on-chip self-programming with boot swapping and flash shield window protection. Programming is performed via Renesas Flash Programmer or compatible tools using the same SWD interface - no external programmer hardware is required for development or field updates. The R5F104JDAFA#10 includes built-in ROM-based bootloader for factory or field firmware recovery.
R5F104JDAFA#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 52-LQFP
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- LVD, POR, PWM, WDT
- Number of I/O:
- 42
- Program Memory Size:
- 48KB (48K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 5.5K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 12x8/10b; D/A 2x8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104JDAFA#10 FAQ
1.How can I place an order for R5F104JDAFA#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104JDAFA#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104JDAFA#10 reliable?
The price and inventory of R5F104JDAFA#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104JDAFA#10 is usually 5 days.
3.What payment methods are accepted for R5F104JDAFA#10?
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Once your R5F104JDAFA#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104JDAFA#10?
For technical support, including R5F104JDAFA#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104JDAFA#10 requirements.
6.How does Aetrix verify that R5F104JDAFA#10 is sourced from the original manufacturer or authorized distributors?
All R5F104JDAFA#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104JDAFA#10 meets industry standards.
7.What is the process for return or replacement of R5F104JDAFA#10?
All R5F104JDAFA#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104JDAFA#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104JDAFA#10 part is unused and in its original packaging.
Return procedure for R5F104JDAFA#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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