Renesas R5F104JHAFA#V0
- Part No.:
- R5F104JHAFA#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 52-LQFP
- Datasheet:
-
R5F104JHAFA#V0.pdf
- Description:
- IC MCU 16BIT 192KB FLASH 52LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,639
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F104JHAFA#V0 from Renesas is a 52-pin LQFP-0.65 mm pitch, industrial-grade RL78/G14 16-bit MCU with 192 KB flash, 20 KB RAM, and 8 KB data flash, operating from 1.6 V to 5.5 V at -40°C to +85°C. It delivers 44 DMIPS at 32 MHz, features ultra-low power consumption (66 μA/MHz active, 0.60 μA RTC+LVD), and integrates 12-bit ADC (20 channels), dual DAC, RTC, and multiple serial interfaces for embedded control in metering and sensor nodes.
For engineers reviewing the R5F104JHAFA#V0 datasheet, R5F104JHAFA#V0 pinout, R5F104JHAFA#V0 application, or R5F104JHAFA#V0 equivalent, key selection criteria include its 52-pin LQFP package with 0.65 mm pitch, industrial temperature rating (D-grade), integrated 12-bit interval timer and real-time clock with calendar, and support for background data flash rewriting during program execution.
Technical Context
The R5F104JHAFA#V0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz) to 30.5 μs (32.768 kHz). It includes a Data Transfer Controller (DTC) with chain transfer capability and an Event Link Controller (ELC) enabling direct peripheral-to-peripheral event routing without CPU intervention.
Its memory subsystem comprises 192 KB on-chip code flash (1 KB block size), 8 KB data flash with 1M rewrite cycles and background operation (BGO), and 20 KB RAM. Power management includes HALT, STOP, and SNOOZE modes, plus on-chip POR and 14-level LVD with interrupt/reset selection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC with 3-stage pipeline; enables deterministic timing and low-power mixed-signal control. |
| Max Operating Frequency | 32 MHz; delivers 44 DMIPS for real-time sensor fusion and communication stack execution. |
| Flash Memory | 192 KB code flash + 8 KB data flash; supports self-programming with boot swap and flash shield window. |
| ADC Resolution & Channels | 10-bit resolution, 20 analog input channels; enables simultaneous monitoring of multiple sensors or power rails. |
| Low-Power Modes | HALT (66 μA/MHz), STOP (0.60 μA), SNOOZE; extends battery life in portable and remote IoT endpoints. |
| Operating Voltage Range | 1.6 V to 5.5 V; allows direct interface with 1.8 V, 3.3 V, and 5 V peripherals without level shifters. |
| Temperature Grade | -40°C to +85°C (D-grade); qualified for industrial automation, building controls, and smart meters. |
Pinout & Package
Package: 52-pin LQFP, 10 × 10 mm body, 0.65 mm pitch, exposed pad not applicable (plastic package).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P121/X1 | Crystal oscillator input | Connects to 32.768 kHz crystal for RTC accuracy; enables calendar mode with alarm and correction. |
| P122/X2/EXCLK | Crystal oscillator output / external clock input | Completes RTC crystal circuit or accepts external clock source for synchronous timing. |
| P137/INTP0 | External interrupt input | Dedicated wake-up pin for low-power sleep states; supports edge-triggered interrupt generation. |
| P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 | Multi-function I/O | Provides 1 Hz RTC output, I²C clock, or JTAG trace clock-configurable per system needs. |
| P60/SCLA0 | I²C bus clock line | Primary I²C interface channel 0 clock; supports standard/fast-mode up to 400 kHz. |
| P61/SDAA0 | I²C bus data line | Primary I²C interface channel 0 data; enables communication with EEPROMs, sensors, and PMICs. |
| P120/ANI19/VCOUT0 | Analog input / voltage comparator output | Supports analog sensing or comparator-based threshold detection with internal reference selection. |
| P147/ANI18/VCOUT1 | Analog input / voltage comparator output | Second comparator output channel; enables dual-threshold or window-comparator configurations. |
Key Features
| Feature | Design Value |
|---|---|
| Background Data Flash Operation (BGO) | Enables concurrent program execution and data flash rewriting-critical for firmware updates without system halt. |
| Event Link Controller (ELC) | Routes 19–26 peripheral events directly (e.g., ADC end-of-conversion → DMA trigger), eliminating CPU polling overhead. |
| Real-Time Clock with Calendar | 99-year calendar, alarm, and clock correction functions-supports time-stamped logging and scheduled wake-up. |
| On-chip Voltage Detector (LVD) | 14 programmable voltage thresholds with interrupt/reset options-ensures reliable brown-out protection across supply ranges. |
| Simplified SPI (CSI) Interface | Up to 8 CSI channels with flexible frame formats-reduces external component count for display, sensor, and memory interfaces. |
Applications
| Smart Energy Metering | Industrial Sensor Node |
|---|---|
Use Scenario: Residential electricity/water/gas meter with tamper detection, pulse counting, and wireless reporting. IC Role / Device Role / Timing Role: Main controller managing metrology ADC sampling, RTC-based billing intervals, and sub-GHz RF communication timing. Use Value: 10-bit ADC with 20 channels captures multiple sensor inputs simultaneously; BGO enables secure firmware updates over-the-air without service interruption. |
Use Scenario: Battery-powered vibration/temperature/humidity node in factory predictive maintenance systems. IC Role / Device Role / Timing Role: Low-power host processor acquiring sensor data via I²C/CSI, executing local FFT preprocessing, and scheduling BLE transmissions. Use Value: 0.60 μA STOP mode with RTC wake-up extends 2-AA battery life beyond 5 years; ELC reduces CPU wake-ups by 70% during periodic sampling. |
| Home Appliance Control | Building Automation Panel |
Use Scenario: Washing machine main board controlling motor drivers, water valves, user interface, and safety interlocks. IC Role / Device Role / Timing Role: Central MCU coordinating PWM motor control, touch-key scanning, and fault-safe shutdown sequences. Use Value: Dual DAC outputs drive analog front-end references; 12-bit interval timer ensures precise motor commutation timing independent of CPU load. |
Use Scenario: HVAC zone controller interfacing with thermostats, dampers, CO₂ sensors, and BACnet MS/TP networks. IC Role / Device Role / Timing Role: Protocol gateway translating Modbus RTU to BACnet MSTP while maintaining real-time environmental logging. Use Value: UART/LIN support enables legacy device integration; 192 KB flash accommodates dual protocol stacks and field-upgradable configuration profiles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104JGAFA#V0 | Same 52-pin LQFP package, but 256 KB flash / 24 KB RAM / 8 KB data flash; higher memory density. | Better suited for applications requiring larger firmware (e.g., multi-protocol gateways or OTA update buffers). | Select when future firmware growth or dual-bank bootloading is required; identical pinout and peripheral set. |
| R5F104JHAFB#V0 | Same flash/RAM/data flash specs, but 48-pin LFQFP (7×7 mm, 0.5 mm pitch); smaller footprint, fewer I/Os (42 vs 46 GPIO). | Preferred for space-constrained designs where I/O count and package height are critical (e.g., portable medical devices). | Choose for PCB area reduction; verify I/O mapping compatibility-some pins (e.g., P76, P77) are absent in 48-pin variant. |
Compared with R5F104JGAFA#V0, the R5F104JHAFA#V0 trades 64 KB flash and 4 KB RAM for lower cost and sufficient capacity for most metering and sensor firmware; versus R5F104JHAFB#V0, it provides 4 additional GPIOs and full 52-pin peripheral access at the expense of board area.
Availability
R5F104JHAFA#V0 is available at Aetrix Electronics and suitable for smart metering, industrial sensor nodes, and home appliance control requiring stable component supply, long-term industrial qualification, and seamless migration from legacy RL78/G13 platforms.
Supply support for R5F104JHAFA#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G14 product line targets cost-sensitive, ultra-low-power general-purpose embedded applications-designed to replace legacy 8/16-bit MCUs with enhanced integration, security, and energy efficiency.
FAQ
What is the maximum operating frequency and core performance of the R5F104JHAFA#V0?
The R5F104JHAFA#V0 operates at up to 32 MHz and delivers 44 DMIPS using the RL78 16-bit CISC core with 3-stage pipeline. Its minimum instruction execution time is 0.03125 μs at 32 MHz with the high-speed on-chip oscillator enabled, making it suitable for real-time control loops and communication stack processing in the R5F104JHAFA#V0.
Does the R5F104JHAFA#V0 support background data flash rewriting?
Yes, the R5F104JHAFA#V0 supports Background Operation (BGO) for data flash, allowing program execution from code flash while rewriting data flash memory. This enables safe firmware updates and parameter storage without halting application logic-a key capability confirmed in the R5F104JHAFA#V0 datasheet Section 1.1.
What are the supported serial communication interfaces on the R5F104JHAFA#V0?
The R5F104JHAFA#V0 integrates Simplified SPI (CSI) across 3–8 channels, UART/LIN across 3–4 channels, and I²C/simplified I²C across 4–10 channels. All interfaces are configurable via peripheral I/O redirection registers, and LIN compliance is explicitly documented for UART channels in the R5F104JHAFA#V0 datasheet.
What is the industrial temperature range and qualification grade for the R5F104JHAFA#V0?
The R5F104JHAFA#V0 is rated for -40°C to +85°C ambient operation and carries the 'D' grade designation per Renesas ordering nomenclature, indicating qualification for industrial applications. This grade includes extended reliability testing and screening per industrial standards, as defined in the R5F104JHAFA#V0 datasheet Section 1.2.
How many analog-to-digital converter (ADC) channels and what resolution does the R5F104JHAFA#V0 provide?
The R5F104JHAFA#V0 features a 10-bit resolution successive-approximation ADC with up to 20 analog input channels, operating across the full 1.6 V to 5.5 V supply range. It includes an internal 1.45 V reference and on-chip temperature sensor-specifications fully confirmed in the R5F104JHAFA#V0 datasheet Section 1.1.
R5F104JHAFA#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 52-LQFP
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 38
- Program Memory Size:
- 192KB (192K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 20K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 12x8/10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104JHAFA#V0 FAQ
1.How can I place an order for R5F104JHAFA#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104JHAFA#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104JHAFA#V0 reliable?
The price and inventory of R5F104JHAFA#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104JHAFA#V0 is usually 5 days.
3.What payment methods are accepted for R5F104JHAFA#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104JHAFA#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104JHAFA#V0?
R5F104JHAFA#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104JHAFA#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104JHAFA#V0?
For technical support, including R5F104JHAFA#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104JHAFA#V0 requirements.
6.How does Aetrix verify that R5F104JHAFA#V0 is sourced from the original manufacturer or authorized distributors?
All R5F104JHAFA#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104JHAFA#V0 meets industry standards.
7.What is the process for return or replacement of R5F104JHAFA#V0?
All R5F104JHAFA#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104JHAFA#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104JHAFA#V0 part is unused and in its original packaging.
Return procedure for R5F104JHAFA#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F104JHAFA#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

