Renesas R5F104LHAFP#V0
- Part No.:
- R5F104LHAFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F104LHAFP#V0.pdf
- Description:
- IC MCU 16BIT 192KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F104LHAFP#V0 from Renesas is a 64-pin LQFP-0.65mm-pitch RL78/G14 16-bit microcontroller with 128 KB flash, 8 KB data flash, 16 KB RAM, 10-bit ADC (16 channels), and integrated RTC, operating from 1.6–5.5 V at –40 to +85°C for industrial control and sensor interface applications.
For engineers reviewing the R5F104LHAFP#V0 datasheet, R5F104LHAFP#V0 pinout, R5F104LHAFP#V0 application, or R5F104LHAFP#V0 equivalent, key selection criteria include ultra-low-power HALT/STOP modes (0.60 μA RTC+LVD), on-chip debug support, 32 MHz max CPU speed (44 DMIPS), and peripheral flexibility via ELC/DTC for deterministic real-time response in resource-constrained embedded systems.
Technical Context
The R5F104LHAFP#V0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz) to 30.5 μs (32.768 kHz), and includes multiply/divide/accumulate instructions within a 1 MB address space. It integrates a configurable 16-bit Timer Array Unit (TAU) with up to 8 channels plus dedicated RTC, watchdog, and interval timers.
Peripheral integration includes 3 UART/LIN channels, 4–10 I²C interfaces, 3–8 CSI/SPI channels, 8–20-channel 10-bit ADC with internal 1.45 V reference and temperature sensor, and dual 8-bit DAC outputs with real-time update capability - all managed via Event Link Controller (ELC) for hardware-triggered, low-latency signal chaining without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline, 44 DMIPS @ 32 MHz |
| Flash Memory | 128 KB code flash with 1 KB block erase, security lock, and self-programming with boot swap |
| Data Flash | 8 KB background operation (BGO) capable, 1M rewrite cycles, programmable at 1.8–5.5 V |
| RAM | 16 KB on-chip SRAM, including dedicated areas for flash library use (start address FE900H) |
| ADC | 10-bit resolution, 16 analog inputs, internal 1.45 V reference, and integrated temperature sensor |
| Power Modes | HALT (66 μA/MHz), STOP (0.60 μA w/ RTC+LVD), SNOOZE - enabling battery-powered multi-year operation |
| Operating Range | 1.6–5.5 V supply, –40 to +85°C ambient (industrial-grade D-temp grade) |
Pinout & Package
Package: 64-pin LQFP (12 × 12 mm, 0.65 mm pitch), RoHS-compliant, JEDEC standard footprint PLQP0064JA-A.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P121 / X1 | Crystal input | Connects to 32.768 kHz tuning-fork crystal for RTC accuracy and low-power clock source |
| P122 / X2 / EXCLK | Crystal output / external clock input | Drives external crystal; alternatively accepts external clock up to 20 MHz for system timing flexibility |
| P137 / INTP0 | Interrupt input 0 | Dedicated edge-sensitive interrupt pin for fast wake-up from STOP/HALT modes with minimal latency |
| P60 / SCLA0 | I²C bus clock line | Configurable as master/slave SCL for primary I²C interface (channel 0), supports standard/fast mode |
| P61 / SDAA0 | I²C bus data line | Configurable as master/slave SDA for primary I²C interface (channel 0), supports ACK/NACK handling |
| P30 / INTP3 / SCK00 / SCL00 / TRJO0 | Multi-function pin | Default SPI clock (SCK00) or I²C clock (SCL00); also serves as JTAG trace port (TRJO0) for debug visibility |
| P50 / INTP1 / SI00 / RxD0 / TOOLRxD / SDA00 / TRGIOA / (TRJO0) | Multi-function serial I/O | Primary UART receive (RxD0), SPI input (SI00), I²C data (SDA00), and debug trace I/O (TRGIOA) |
| P51 / INTP2 / SO00 / TxD0 / TOOLTxD / TRGIOB | Multi-function serial I/O | Primary UART transmit (TxD0), SPI output (SO00), and debug trace output (TRGIOB) with hardware flow control |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-power operation | 0.60 μA in STOP mode with RTC + LVD active enables >10-year coin-cell battery life in metering applications |
| Hardware event linking (ELC) | 19–26 event sources directly trigger peripherals (e.g., ADC start → DMA transfer → timer compare) without CPU overhead |
| Data flash BGO | Background rewriting allows firmware updates or logging while executing real-time control tasks from main flash |
| On-chip debug & programming | Fully supported via single-wire debug (SWD) interface; no external debugger required for development or field updates |
| Flexible clock system | High-accuracy on-chip oscillator (±1.0% from 1–64 MHz) eliminates external crystal cost for non-RTC functions |
| Peripheral I/O redirection | PIOR0/PIOR1 registers remap up to 16 peripheral functions to alternate pins, simplifying PCB layout and routing |
Applications
| Industrial Sensor Node | Smart Energy Meter |
|---|---|
|
Use Scenario: Battery-powered environmental sensor collecting temperature, humidity, and CO₂ via analog and I²C sensors, transmitting data hourly over LPWAN. IC Role / Device Role / Timing Role: Main system controller managing sensor polling, ADC conversion, RTC-based scheduling, and low-power sleep/wake cycles. Use Value: 0.60 μA STOP mode with RTC ensures precise wake-up intervals and multi-year battery life without external real-time clock IC. |
Use Scenario: Residential electricity meter with tamper detection, pulse counting, and secure data logging across 10+ years of operation. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC sampling, EEPROM-like data flash logging, and secure firmware updates. Use Value: 8 KB data flash with 1M write cycles and BGO enables daily energy accumulation logs without interrupting measurement accuracy. |
| Home Appliance Control | Industrial PLC I/O Module |
|
Use Scenario: Washing machine main board controlling motor drivers, water valves, user interface, and safety interlocks. IC Role / Device Role / Timing Role: Real-time motion control hub coordinating PWM outputs, analog feedback, and fault monitoring via LVD/INTP pins. Use Value: ELC-linked timer-to-ADC triggering ensures synchronized motor current sampling and torque calculation at fixed intervals. |
Use Scenario: DIN-rail mounted digital I/O module converting 24 V DC field signals to Modbus RTU over RS-485. IC Role / Device Role / Timing Role: Protocol processor handling UART framing, CRC generation, and isolated GPIO state scanning with deterministic latency. Use Value: 4 UART/LIN channels support simultaneous Modbus master/slave, diagnostics, and bootloader communication without software buffering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104LGAFP#V0 | Same 64-pin LQFP package, but 96 KB flash, 12 KB RAM, and 8 KB data flash | Suitable for simpler control tasks with smaller firmware footprint and reduced RAM requirements | Select when application code size remains under 96 KB and memory headroom is not required for future feature expansion |
| R5F104LJAFP#V0 | Same 64-pin LQFP package, 192 KB flash, 20 KB RAM, 8 KB data flash, higher memory density | Better suited for applications requiring larger firmware (e.g., protocol stacks, OTA update buffers) | Choose when firmware growth projection exceeds 128 KB or additional RAM is needed for complex state machines or buffers |
Compared with R5F104LGAFP#V0, the R5F104LHAFP#V0 provides 32 KB more flash and 4 KB more RAM for enhanced feature scalability, while compared with R5F104LJAFP#V0, it offers lower cost and power profile for stable, mature designs without near-term memory expansion needs.
Availability
R5F104LHAFP#V0 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart energy meters, and home appliance control systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for R5F104LHAFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive, battery-operated, and industrial control applications where reliability, code efficiency, and peripheral integration are critical.
FAQ
What is the maximum operating frequency and corresponding DMIPS rating for the R5F104LHAFP#V0?
The R5F104LHAFP#V0 operates at up to 32 MHz with a measured performance of 44 DMIPS. This value is derived from the RL78 CPU core's 3-stage pipeline architecture and confirmed in Renesas' official RL78/G14 datasheet (R01DS0053EJ0370). The R5F104LHAFP#V0 achieves this performance while maintaining ultra-low power consumption - 66 μA per MHz in HALT mode - making it suitable for high-efficiency real-time control applications.
Does the R5F104LHAFP#V0 support background data flash rewriting during program execution?
Yes, the R5F104LHAFP#V0 supports Background Operation (BGO) for its 8 KB data flash memory. This allows the CPU to execute code from main flash while simultaneously erasing or writing to data flash - essential for logging, parameter storage, or firmware updates without interrupting real-time tasks. BGO is enabled via dedicated control registers and requires no external hardware support.
What debug interface does the R5F104LHAFP#V0 provide, and is external hardware required?
The R5F104LHAFP#V0 integrates a single-wire debug (SWD) interface compliant with ARM CoreSight standards, enabling full on-chip debugging, flash programming, and real-time trace without requiring external debug probes beyond a standard SWD adapter. No JTAG header or additional debug circuitry is needed - the interface uses shared pins (e.g., P30/P31/TRJO0/TRJIO0) and is fully supported by Renesas CS+ and e2 studio IDEs.
How many analog input channels does the 10-bit ADC in the R5F104LHAFP#V0 support, and what references are available?
The R5F104LHAFP#V0 features a 10-bit successive-approximation ADC with 16 selectable analog input channels (ANI0–ANI18, excluding reserved pins). It supports both external reference (AVREFP/AVREFM) and internal 1.45 V reference voltage, plus an integrated temperature sensor. All conversions are hardware-triggered via ELC or timer events, ensuring deterministic sampling timing independent of CPU load.
Is the R5F104LHAFP#V0 pin-compatible with other RL78/G14 variants in the same 64-pin LQFP package?
Yes, the R5F104LHAFP#V0 shares identical pinout, electrical characteristics, and package dimensions (PLQP0064JA-A) with all other RL78/G14 64-pin LQFP variants - including R5F104LGAFP#V0, R5F104LJAFP#V0, and R5F104LLAFP#V0. This enables direct PCB reuse across memory-variant SKUs, simplifying design scaling and inventory management without layout changes.
R5F104LHAFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 48
- Program Memory Size:
- 192KB (192K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 20K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 12x8/10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104LHAFP#V0 FAQ
1.How can I place an order for R5F104LHAFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104LHAFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104LHAFP#V0 reliable?
The price and inventory of R5F104LHAFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104LHAFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F104LHAFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104LHAFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104LHAFP#V0?
R5F104LHAFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104LHAFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104LHAFP#V0?
For technical support, including R5F104LHAFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104LHAFP#V0 requirements.
6.How does Aetrix verify that R5F104LHAFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F104LHAFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104LHAFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F104LHAFP#V0?
All R5F104LHAFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104LHAFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104LHAFP#V0 part is unused and in its original packaging.
Return procedure for R5F104LHAFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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