Renesas R5F104LHGFP#30
- Part No.:
- R5F104LHGFP#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F104LHGFP#30.pdf
- Description:
- IC MCU 16BIT 192KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:540
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Product details
Overview
R5F104LHGFP#30 from Renesas is a 64-pin LFQFP, 512 KB flash, 8 KB data flash, 20 KB RAM RL78/G14 16-bit microcontroller operating from 1.6–5.5 V, delivering 44 DMIPS at 32 MHz with ultra-low power consumption (66 μA/MHz active, 0.60 μA RTC+LVD mode), used in industrial sensor nodes and battery-powered control modules.
For engineers reviewing the R5F104LHGFP#30 datasheet, R5F104LHGFP#30 pinout, R5F104LHGFP#30 application, or R5F104LHGFP#30 equivalent, key selection considerations include its 64-pin LFQFP-0.5 mm package, integrated RTC with calendar/alarm, 12-bit interval timer, dual UART/LIN support, and 16-channel 10-bit ADC with internal temperature sensor and 1.45 V reference.
Technical Context
The R5F104LHGFP#30 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 µs (32 MHz high-speed on-chip oscillator) to 30.5 µs (32.768 kHz subsystem clock). It integrates Event Link Controller (ELC) for hardware-triggered peripheral chaining and Data Transfer Controller (DTC) with block/chain transfer modes activated by interrupt sources.
It features dual serial interface sets: three UART/LIN channels (one with LIN bus support), up to ten I²C/simplified I²C channels, and up to eight CSI (SPI-compatible) channels. The analog subsystem includes an 8/10-bit ADC with 16–20 input channels, two 8-bit DAC outputs, and two comparator channels with selectable internal/external reference voltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline and multiply/divide/accumulate instructions |
| Max Clock Speed | 32 MHz - delivers 44 DMIPS; supports 1–64 MHz programmable high-speed on-chip oscillator (±1.0% accuracy) |
| Memory | 512 KB code flash (1 KB blocks), 8 KB data flash (1M rewrite cycles), 20 KB SRAM |
| Power Modes | Halt (66 μA/MHz), Stop (0.60 μA with RTC + LVD), Snooze - enables rapid wake-up from low-power states |
| Analog Peripherals | 10-bit ADC (20 ch, 1.45 V ref, temp sensor), dual 8-bit DAC (0–VDD output), two comparators (window/high/low-speed modes) |
| Timers | 12× 16-bit timers (TAU/Timer RJ/RD/RG), 1× 12-bit interval timer, 1× RTC (99-year calendar, alarm, correction), 1× watchdog |
| Serial Interfaces | 3× UART/LIN (1 with LIN support), 4–10× I²C/simplified I²C, 3–8× CSI (SPI-compatible), 1× SSI |
| Operating Temp | −40°C to +105°C (Industrial G-grade) - qualified for extended-temperature industrial environments |
Pinout & Package
Package: 64-pin LFQFP, 10 × 10 mm body, 0.5 mm pitch, exposed pad not present (LFQFP variant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00–P01 | General-purpose I/O / Analog inputs (ANI17/ANI16) | Support TTL input buffer, N-ch open drain, on-chip pull-up; enable 1.8/2.5/3 V level shifting |
| P10–P17 | Multifunction pins (SCK11/SI11/SO11, UART2, I²C1, TRDIOx, IVREF/IVCMP) | Configurable via PIOR0/1 registers; support LIN-compliant UART2, hardware CRC, and comparator reference routing |
| P120–P147 | Analog peripherals (VCOUT0/VCOUT1, ANI19/ANI18) | Integrated voltage-controlled oscillator outputs and auxiliary analog inputs for sensor biasing or calibration |
| P30–P31 | Interrupt/timer I/O (INTP3/INTP4, TI03/TO03, RTC1HZ) | RTC 1 Hz output and edge-triggered interrupts enable precise time-synchronized event handling without CPU polling |
| P60–P62 | I²C/SSI interface (SCLA0/SDAA0/SSI00) | Dedicated hardware I²C master/slave with clock stretching and SSI for SPI-like synchronous serial communication |
| P121–P124 | Crystal oscillator inputs (X1/X2, XT1/XT2/EXCLKS) | Support external crystal (32.768 kHz for RTC, 1–20 MHz for main clock) or external clock source with fail-safe switching |
| REGC, VDD, VSS, RESET | Power management and reset | REGC requires 0.47–1 µF capacitor to VSS; internal POR and 14-level LVD with interrupt/reset selectability |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low power HALT/STOP/SNOOZE modes | Enables <0.6 µA retention with RTC + LVD active - critical for multi-year battery operation in remote sensors |
| Background data flash rewriting (BGO) | Allows full program execution from flash while updating non-volatile configuration/data - no runtime interruption required |
| Event Link Controller (ELC) | Hardware-peripheral linking eliminates CPU overhead for time-critical sequences (e.g., ADC trigger → DMA → interrupt) |
| On-chip debug with boot swapping | Enables safe firmware updates via dual-bank flash layout and real-time debugging without external JTAG emulator |
| 10-bit ADC with internal temp sensor & 1.45 V ref | Eliminates need for external reference or temperature IC in thermal monitoring and compensation applications |
| LIN-compliant UART channel | Meets ISO 17987-4 physical layer requirements - supports automotive body electronics and industrial sub-networks |
Applications
| Industrial Sensor Node | Smart HVAC Actuator |
|---|---|
Use Scenario: Battery-powered wireless temperature/humidity/pressure node with local logging and BLE gateway interface. IC Role / Device Role / Timing Role: Main controller managing sensor acquisition (ADC/DAC/comparator), RTC-based sampling schedule, and low-power sleep/wake cycles. Use Value: 0.60 μA STOP mode extends 2xAA battery life beyond 5 years; integrated 1.45 V reference and temp sensor reduce BOM count by two components. | Use Scenario: Motorized damper control module receiving commands over LIN bus and regulating position via PWM-driven actuator. IC Role / Device Role / Timing Role: LIN slave node executing closed-loop position control using Timer RD for PWM generation and ELC-triggered ADC feedback sampling. Use Value: Native LIN-compliant UART eliminates transceiver IC; 16-bit TAU timers provide 0.1% duty-cycle resolution at 25 kHz PWM frequency. |
| Programmable Logic Controller (PLC) I/O Module | Energy Meter Front-End |
Use Scenario: DIN-rail mounted digital I/O expansion module with opto-isolated inputs/outputs and Modbus RTU over RS-485. IC Role / Device Role / Timing Role: Protocol handler and GPIO manager interfacing with RS-485 transceiver, opto drivers, and status LEDs via DTC-assisted UART transfers. Use Value: DTC offloads UART byte transfers from CPU during Modbus frame reception/transmission, freeing CPU for logic scanning. | Use Scenario: Residential smart meter measuring voltage/current via shunt/CT, computing kWh, and reporting via NB-IoT or PLC. IC Role / Device Role / Timing Role: Analog front-end controller acquiring synchronized voltage/current samples via ADC, performing RMS/calibration math, and managing secure data flash storage. Use Value: Background data flash rewriting allows firmware updates without interrupting metering; 1M-cycle endurance supports 10+ years of daily log writes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104LJGFP#30 | Same 64-pin LFQFP package, 192 KB flash, 8 KB data flash, 20 KB RAM - reduced code density but identical peripheral set and pinout | Suitable where firmware size < 192 KB; lower cost for legacy or less feature-rich designs | Select when full 512 KB flash is unnecessary and BOM cost optimization is prioritized over future firmware headroom |
| R5F104LLGFP#30 | Same 64-pin LFQFP package, 384 KB flash, 8 KB data flash, 32 KB RAM - intermediate memory tier with larger SRAM for complex buffers or stacks | Better suited for applications requiring larger protocol stacks (e.g., MQTT over TLS) or real-time FFT-based analytics | Choose when >20 KB RAM is needed for multi-threaded FreeRTOS tasks or large communication buffers without external RAM |
Compared with R5F104LJGFP#30 and R5F104LLGFP#30, the R5F104LHGFP#30 provides maximum on-chip code capacity (512 KB) and balanced RAM (20 KB), making it optimal for field-upgradable industrial firmware with integrated safety diagnostics and dual-bank OTA capability.
Availability
R5F104LHGFP#30 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart HVAC actuators, PLC I/O modules, and energy meter front-ends requiring stable component supply across long production lifecycles.
Supply support for R5F104LHGFP#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive, battery-operated, and thermally constrained industrial control applications - emphasizing ultra-low active/idle current and integrated analog functionality.
FAQ
What is the maximum operating frequency and associated performance of the R5F104LHGFP#30?
The R5F104LHGFP#30 operates up to 32 MHz using its high-accuracy on-chip oscillator (±1.0% over −40°C to +105°C), delivering 44 DMIPS. Its 3-stage pipeline RL78 core supports minimum instruction execution times from 0.03125 µs (32 MHz) down to 30.5 µs (32.768 kHz), enabling dynamic clock scaling for power/performance trade-offs in the R5F104LHGFP#30.
Does the R5F104LHGFP#30 support LIN bus communication, and which peripheral implements it?
Yes, the R5F104LHGFP#30 supports LIN bus communication via UART2 - one of its three UART channels explicitly qualified for LIN 2.2A/ISO 17987-4 compliance. This channel includes break-detection, sync-field processing, and checksum calculation hardware, enabling direct connection to a LIN transceiver without external protocol assist, as confirmed in the R5F104LHGFP#30 datasheet Section 1.1.
What are the data flash endurance and voltage requirements for rewriting the R5F104LHGFP#30?
The R5F104LHGFP#30 features 8 KB of data flash rated for 1,000,000 write/erase cycles (typical) with operation supported across the full VDD range of 1.8–5.5 V. Rewrites can occur in background (BGO mode) while code executes from main flash, and the flash library reserves fixed RAM regions (e.g., F3F00H start address for R5F104xL variants) - all verified in the R5F104LHGFP#30's Flash Self-Programming Library documentation.
How does the Event Link Controller (ELC) enhance real-time response in the R5F104LHGFP#30?
The ELC in the R5F104LHGFP#30 enables hardware-level linking of 19–26 peripheral events (e.g., timer overflow → ADC start → DTC transfer → interrupt), eliminating CPU intervention and reducing latency to sub-microsecond levels. This allows deterministic, jitter-free signal chains - such as synchronized ADC sampling triggered by PWM edges - without software overhead, a capability confirmed in the R5F104LHGFP#30's ELC functional description.
What is the analog input channel count and reference configuration for the ADC in the R5F104LHGFP#30?
The R5F104LHGFP#30 integrates a 10-bit successive-approximation ADC with up to 20 analog input channels (ANI0–ANI19), supporting both internal 1.45 V reference and external reference inputs. It includes an on-chip temperature sensor and AVREFP/AVREFM differential reference pins, allowing ratiometric or absolute measurements - specifications directly listed in the R5F104LHGFP#30's "A/D Converter" feature table.
R5F104LHGFP#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Last Time Buy
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 48
- Program Memory Size:
- 192KB (192K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 20K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 5.5V
- Data Converters:
- A/D 12x8/10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104LHGFP#30 FAQ
1.How can I place an order for R5F104LHGFP#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104LHGFP#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104LHGFP#30 reliable?
The price and inventory of R5F104LHGFP#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104LHGFP#30 is usually 5 days.
3.What payment methods are accepted for R5F104LHGFP#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104LHGFP#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104LHGFP#30?
R5F104LHGFP#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104LHGFP#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104LHGFP#30?
For technical support, including R5F104LHGFP#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104LHGFP#30 requirements.
6.How does Aetrix verify that R5F104LHGFP#30 is sourced from the original manufacturer or authorized distributors?
All R5F104LHGFP#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104LHGFP#30 meets industry standards.
7.What is the process for return or replacement of R5F104LHGFP#30?
All R5F104LHGFP#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104LHGFP#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104LHGFP#30 part is unused and in its original packaging.
Return procedure for R5F104LHGFP#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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