Renesas R5F1054AASP#10
- Part No.:
- R5F1054AASP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 16-SSOP (0.173", 4.40mm Width)
- Datasheet:
-
R5F1054AASP#10.pdf
- Description:
- IC MCU 16BIT 16KB FLASH 16SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F1054AASP#10 from Renesas Electronics is a 16-pin RL78/G11 16-bit microcontroller designed for ultra-low-power general-purpose embedded control. It integrates 16 KB code flash, 2 KB data flash, and 1.5 KB RAM; operates from 1.6 V to 5.5 V; delivers 33 DMIPS at 24 MHz; and supports true low-power modes (58.3 μA/MHz active, 0.64 μA STOP). It is used in battery-powered sensor nodes, smart home controllers, and industrial monitoring modules requiring reliable mixed-signal integration.
For engineers reviewing the R5F1054AASP#10 datasheet, R5F1054AASP#10 pinout, R5F1054AASP#10 application, or R5F1054AASP#10 equivalent, key selection considerations include its 16-pin SSOP package, dual UART + quad I²C + dual CSI interfaces, 8-channel 10-bit ADC, dual 8-bit DAC outputs, and support for on-chip debug with flash self-programming - all within a -40°C to +85°C consumer-grade temperature range.
Technical Context
The R5F1054AASP#10 implements the RL78 CPU core with CISC architecture, 3-stage pipeline, and configurable instruction execution time (0.04167 μs at 24 MHz high-speed on-chip oscillator). It features a multi-clock system with selectable high-speed (up to 24 MHz), middle-speed (4/2/1 MHz), and low-speed (15 kHz) on-chip oscillators, plus external crystal support (1–20 MHz).
Its peripheral set includes a 4-channel 16-bit Timer Array Unit (TAU), 12-bit interval timer, watchdog timer, Data Transfer Controller (DTC) with 22 activation sources, Event Link Controller (ELC) with 16 event inputs, and dual independent serial array units supporting UART, CSI, and simplified I²C protocols - enabling deterministic real-time peripheral coordination without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC CPU with 3-stage pipeline and multiply/divide/accumulate instructions |
| Operating Voltage | 1.6 V to 5.5 V - enables direct interface with 1.8 V, 2.5 V, 3.0 V, and 5 V logic domains |
| Flash Memory | 16 KB code flash + 2 KB data flash with background operation (BGO) and 1M rewrite cycles |
| Analog Peripherals | 10-bit ADC (8 channels), dual 8-bit DAC (ANO1 & comparator output), 2-channel comparator, 1-channel PGA |
| Serial Interfaces | 2 × UART, 4 × simplified I²C (including 2 multimaster), 2 × CSI - all configurable via PIOR registers |
| Power Modes | HALT (58.3 μA/MHz), STOP (0.64 μA), SNOOZE - optimized for intermittent sensing and wake-on-event |
| Package & Pin Count | 16-pin plastic SSOP (4.4 × 5.0 mm, 0.65-mm pitch) with 13 CMOS I/O pins and 4 dedicated analog/oscillator pins |
Pinout & Package
Package: 16-pin plastic SSOP (PRSP0016JC-B), 4.4 × 5.0 mm body, 0.65-mm lead pitch, RoHS-compliant, tape-and-reel (#10, #30, #50, #70).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P125/RESET/INTP9 | Reset input / External interrupt 9 | Active-low hardware reset with glitch filter; doubles as edge-triggered interrupt source |
| P122/X2/EXCLK/SI10/RxD1/TI02/INTP1 | Crystal input / External clock / SPI input / UART1 RX / Timer input / Interrupt 1 | Multi-function pin supporting main system clock source selection and dual peripheral routing |
| P121/X1/(TI01)/INTP2 | Crystal input / Optional timer input / Interrupt 2 | Primary crystal oscillator connection; TI01 function enabled only via PIOR register configuration |
| P137/INTP0/TI03 | External interrupt 0 / Timer input 3 | Dedicated high-priority interrupt input with configurable sensitivity; also serves as TAU channel trigger |
| REGC | Regulator capacitance terminal | Must be connected to VSS via 0.47–1 μF capacitor to stabilize internal voltage regulator output |
| VSS | Ground reference | Primary digital ground; must be low-impedance connection shared with REGC capacitor |
| VDD | Power supply | 1.6–5.5 V main supply; powers core, flash, RAM, and all digital peripherals |
| P20/ANI0/AVREFP/IVREF1/SO10/TxD1 | Analog input 0 / ADC reference + / Comparator ref 1 / SPI output / UART1 TX | Shared analog/digital pin with programmable function assignment; AVREFP sets ADC reference top rail |
| P21/ANI1/AVREFM/IVREF0 | Analog input 1 / ADC reference – / Comparator ref 0 | Provides differential ADC reference and dual comparator reference points; AVREFM = AVSS when unconnected |
| P22/ANI2/PGAI/IVCMP0 | Analog input 2 / PGA input / Comparator 0 input | Direct connection to programmable gain amplifier and comparator; supports single-ended or differential sensing |
| P23/ANI3/ANO1/PGAGND | Analog input 3 / DAC output / PGA ground | Delivers 8-bit DAC output (0–VDD) on ANO1; PGAGND provides dedicated low-noise return for PGA |
| P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/TxD0/PCLBUZ0/TKBO1/SDAA0 | Analog input 21 / Key return 1 / Timer input 0 / Timer output 1 / Interrupt 3 / I²C clock / UART0 TX / Buzzer / TMKB output / I²C data | High-density multiplexed pin supporting up to 11 functions; SCK11/SCL11/SDAA0 enable full I²C master/slave operation |
| P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/RxD0/SI11/SDA11/SCLA0 | Analog input 20 / Key return 0 / Timer input 1 / Timer output 0 / Interrupt 4 / TMKB output / UART0 RX / SPI input / I²C data / I²C clock | Enables simultaneous UART0, CSI11, and I²C (SCLA0/SDA11) communication; KR0/KR1 support matrix keypad scanning |
| P33/ANI18/IVCMP1/INTP11 | Analog input 18 / Comparator 1 input / Interrupt 11 | Comparator 1 input with dedicated interrupt vector; supports window mode detection with IVCMP0/IVCMP1 |
| P40/TOOL0/TO03/(PCLBUZ0)/SCK10/VCOUT0/VCOUT1/INTFO | Tool interface / Timer output 3 / Optional buzzer / SPI clock / Comparator outputs / Interrupt flag | VCOUT0/VCOUT1 provide direct comparator output signals; INTFO allows hardware flagging of interrupt events to external logic |
| P56/ANI22/KR2/SO11/INTP10/(TO03)/(INTFO) | Analog input 22 / Key return 2 / SPI output / Interrupt 10 / Optional timer output / Optional interrupt flag | Supports 3-key matrix scan (KR0–KR2); SO11 enables daisy-chain SPI slave configurations |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low power consumption | 58.3 μA/MHz active current and 0.64 μA STOP mode enable >10-year battery life in periodic sensing applications |
| On-chip debug & self-programming | Integrated on-chip debug interface and flash shield window allow secure firmware updates without external programmer |
| Flexible clock system | Three independent on-chip oscillators (24 MHz HS, 4 MHz MS, 15 kHz LS) eliminate need for external crystals in cost-sensitive designs |
| Hardware-accelerated peripherals | DTC and ELC offload CPU from data movement and event synchronization - reducing ISR latency by up to 70% |
| Mixed-signal integration | Single-chip solution with 8-channel ADC, dual DAC, 2 comparators, PGA, and temperature sensor reduces BOM count by ≥4 discrete components |
| Robust I/O architecture | N-ch open-drain, TTL input, and on-chip pull-up options per port pin simplify level-shifting and reduce external biasing components |
Applications
| Smart Thermostat Control | Industrial Sensor Node |
|---|---|
|
Use Scenario: Local temperature/humidity regulation with wireless reporting and user interface feedback. IC Role / Device Role / Timing Role: Main system controller executing PID loop, managing LCD/buzzer output, and handling BLE/Wi-Fi co-processor handshaking via UART. Use Value: Integrated 8-bit DAC drives piezo buzzer directly; 10-bit ADC reads thermistor/HTS221 via I²C; STOP mode extends coin-cell battery life to 5+ years. |
Use Scenario: Remote vibration/temperature monitoring in factory equipment using LoRaWAN backhaul. IC Role / Device Role / Timing Role: Signal acquisition engine sampling accelerometer and thermistor at 100 Hz, performing FFT preprocessing, and triggering LoRa transmission on threshold breach. Use Value: DTC transfers ADC results to RAM while CPU sleeps; ELC synchronizes timer-triggered sampling with comparator-based wake events; 1.6 V operation supports energy-harvesting power supplies. |
| Home Appliance Motor Control | Medical Wearable Monitor |
|
Use Scenario: Brushless DC motor commutation and fault protection in compact kitchen appliances. IC Role / Device Role / Timing Role: Real-time motor phase timing generator using TAU PWM outputs, current sensing via ADC, and overtemperature shutdown via comparator. Use Value: TAU channels generate complementary PWM with dead-time insertion; 12-bit interval timer ensures precise 20 kHz switching frequency; PGAI amplifies shunt voltage for accurate current measurement. |
Use Scenario: Continuous heart rate and SpO₂ monitoring using photoplethysmography (PPG) with optical sensors. IC Role / Device Role / Timing Role: Analog front-end controller digitizing PPG signals, applying digital filtering, and transmitting processed data via UART to Bluetooth SoC. Use Value: Dual DAC outputs drive LED current sources with 256-step resolution; PGA provides 1–16× programmable gain for ambient light rejection; 0.64 μA STOP mode minimizes quiescent drain during sleep intervals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F1054AGSP#10 | Same die, industrial-grade (-40°C to +105°C) temperature rating; identical electrical specs and pinout | Required for applications operating beyond +85°C ambient (e.g., under-hood automotive, industrial enclosures) | Select R5F1054AGSP#10 when extended temperature qualification is mandatory; otherwise R5F1054AASP#10 suffices for consumer-grade environments. |
| RL78/G13 R5F109A8ASP#30 | Higher memory (64 KB flash, 6 KB RAM), additional peripherals (USB, CAN, more timers), 20-pin LSSOP package | Targeted at feature-rich applications needing USB connectivity, larger firmware, or CAN bus integration | Choose R5F109A8ASP#30 only if memory headroom or USB/CAN functionality is required; R5F1054AASP#10 offers optimal cost/performance for basic control tasks. |
Compared with R5F1054AGSP#10, the R5F1054AASP#10 trades extended temperature range for lower unit cost and qualification overhead; compared with R5F109A8ASP#30, it provides leaner resource allocation and smaller footprint for cost-sensitive, low-complexity embedded systems.
Availability
R5F1054AASP#10 is available at Aetrix Electronics and suitable for smart thermostat control, industrial sensor nodes, home appliance motor control, medical wearable monitors, and battery-powered IoT edge devices requiring stable component supply across production lifecycles.
Supply support for R5F1054AASP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets, with annual revenue exceeding $10 billion.
The RL78/G11 product line targets cost-sensitive, ultra-low-power general-purpose control applications - emphasizing minimal external components, integrated analog peripherals, and seamless migration from 8-bit platforms.
FAQ
What is the maximum operating frequency of the R5F1054AASP#10?
The R5F1054AASP#10 supports a maximum system clock frequency of 24 MHz using its high-speed on-chip oscillator. When driven by an external crystal, the maximum supported frequency is 20 MHz (at VDD ≥ 2.7 V), 16 MHz (at VDD ≥ 2.4 V), 8 MHz (at VDD ≥ 1.8 V), or 4 MHz (at VDD ≥ 1.6 V). The R5F1054AASP#10 achieves 33 DMIPS at 24 MHz operation.
Does the R5F1054AASP#10 support in-system programming (ISP)?
Yes, the R5F1054AASP#10 supports in-system programming via its on-chip debug interface and self-programming capability. It includes boot swap functionality and flash shield window protection, allowing secure firmware updates in the field without removing the R5F1054AASP#10 from the PCB.
How many analog input channels does the R5F1054AASP#10 have?
The R5F1054AASP#10 provides 8 external analog input channels (ANI0–ANI3, ANI18, ANI20–ANI22) and one internal temperature sensor channel. Its 10-bit A/D converter supports simultaneous sampling across these inputs with programmable reference voltages (AVREFP/AVREFM) and built-in sample-and-hold.
What serial communication interfaces are integrated into the R5F1054AASP#10?
The R5F1054AASP#10 integrates two UART channels, four simplified I²C channels (two of which support multimaster operation), and two CSI (simplified SPI) channels. All interfaces are software-configurable and share pins via the Peripheral I/O Redirection Registers (PIOR0–PIOR3).
Is the R5F1054AASP#10 pin-compatible with other RL78/G11 variants?
The R5F1054AASP#10 is pin-compatible with other 16-pin RL78/G11 variants in the same package type (SSOP), including R5F1054AGSP#10 and R5F1054AANA#00 (HWQFN). However, pin functions may differ between SSOP and HWQFN packages due to distinct pin mappings - always verify against the specific variant's pin configuration diagram before board layout.
R5F1054AASP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 16-SSOP (0.173", 4.40mm Width)
- Series:
- RL78/G11
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 24MHz
- Connectivity:
- CSI, I2C, UART/USART
- Peripherals:
- LVD, POR, WDT
- Number of I/O:
- 9
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 2K x 8
- RAM Size:
- 1.5K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 9x10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F1054AASP#10 FAQ
1.How can I place an order for R5F1054AASP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F1054AASP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F1054AASP#10 reliable?
The price and inventory of R5F1054AASP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F1054AASP#10 is usually 5 days.
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Once your R5F1054AASP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F1054AASP#10?
For technical support, including R5F1054AASP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F1054AASP#10 requirements.
6.How does Aetrix verify that R5F1054AASP#10 is sourced from the original manufacturer or authorized distributors?
All R5F1054AASP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F1054AASP#10 meets industry standards.
7.What is the process for return or replacement of R5F1054AASP#10?
All R5F1054AASP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F1054AASP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F1054AASP#10 part is unused and in its original packaging.
Return procedure for R5F1054AASP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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