Renesas R5F10NMGDFB#35
- Part No.:
- R5F10NMGDFB#35
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
R5F10NMGDFB#35.pdf
- Description:
- IC MCU 16BIT 128KB FLASH 80LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F10NMGDFB#35 from Renesas is an 80-pin RL78/I1C 16-bit microcontroller designed for electric AMI power meter applications, featuring 128 KB code flash, 2 KB data flash, 8 KB RAM, hardware AES encryption, and independent-power-supply RTC. It operates from 1.9 V to 5.5 V, supports HALT/STOP/SNOOZE low-power modes, and integrates a 24-bit ΔΣ A/D converter with four channels.
For engineers reviewing the R5F10NMGDFB#35 datasheet, R5F10NMGDFB#35 pinout, R5F10NMGDFB#35 application, or R5F10NMGDFB#35 equivalent, this page delivers verified technical context, package mapping, real-world use cases in utility metering, and validated alternative options - all grounded in Renesas' official R01DS0281EJ0231 Rev.2.31 documentation.
Technical Context
The R5F10NMGDFB#35 implements the RL78 CPU core with CISC architecture and 3-stage pipeline, supporting instruction execution times from 0.03125 µs (32 MHz PLL) to 66.6 µs (15 kHz low-speed oscillator). Its on-chip peripherals include eight 16-bit timer channels, one 12-bit interval timer, four 8-bit interval timers, and an independent-power-supply RTC with calendar, alarm, and clock correction functions.
It integrates dual A/D subsystems: a 24-bit ΔΣ ADC (3-channel in 80-pin variants per datasheet Table 1-1 and Section 1.5.2), and an 8/10-bit SAR ADC with six input channels. The device includes hardware AES (GCM/ECB/CBC modes, 128/192/256-bit keys), a 32-bit MAC unit, DTC, ELC, and LCD controller supporting up to 34 segments and 8 commons - all optimized for secure, ultra-low-power metering firmware execution.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC CPU with 3-stage pipeline; enables deterministic real-time control in meter firmware with minimal power overhead. |
| Flash Memory | 128 KB code flash + 2 KB data flash; supports background operation (BGO) and 1M write cycles for secure firmware updates and tariff storage. |
| RAM | 8 KB on-chip RAM (≈7 KB usable with self-programming); sufficient for AMI protocol stacks (DLMS/COSEM) and real-time data buffering. |
| Operating Voltage | 1.9 V to 5.5 V; accommodates wide battery and line-powered meter supply rails without external regulators. |
| Low-Power Modes | HALT, STOP, SNOOZE; achieves sub-µA RTC-active current, critical for battery-backed meter timekeeping over 10+ years. |
| AES Engine | Hardware GCM/ECB/CBC with 128/192/256-bit keys; accelerates DLMS/COSEM security authentication and encrypted data transmission. |
| ΔΣ A/D Converter | 24-bit resolution, 3-channel (80-pin variant); provides high-accuracy current/voltage sampling for Class 0.2/0.5 electricity metering compliance. |
Pinout & Package
Package: 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch), industrial temperature grade (–40°C to +85°C), tray packaging (Ver.1.1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P07 | TxD0 / TOOLTxD / SEG37 / INTP2 | Primary UART transmit for optical port or PLC communication; also serves as LCD segment driver and interrupt source. |
| P06 | RxD0 / SDA00 / TOOLRxD / SEG36 | UART receive and I²C data line for sensor interface; dual-role pin reduces BOM count in compact meter PCB layouts. |
| P05 | SCK00 / SCL00 / INTP3 / SEG35 | Shared SPI clock and I²C clock for peripheral expansion; supports multi-protocol sensor connectivity with single pin. |
| P125 | VL3 / INTP1 / TI05 / TO05 / PCLBUZ1 | LCD voltage level control and timer I/O; enables precise contrast tuning while providing timing signals for pulse output billing. |
| P62 | TI02 / TO02 / RTCOUT | Dedicated RTC correction clock output (1 Hz/64 Hz); feeds external calibration circuitry or metrology ASIC synchronization. |
| P150 | RTCOUT / RTCIC0 | Primary RTC event capture and correction clock output; essential for time-synchronized load profiling and tariff switching. |
| VDD / EVDD0 | Main / Port Power Supply | Separate power domains allow isolated analog/digital noise management - critical for ΔΣ ADC accuracy in noisy meter environments. |
| VRTC | RTC Backup Power | Accepts coin-cell or supercap input; maintains calendar and alarm during main power failure per IEC 62056 requirements. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Power Supply RTC | Calendar function for 99 years with alarm and clock correction; retains time during main power loss without software intervention. |
| Hardware AES Encryption | GCM/ECB/CBC modes with 128/192/256-bit keys accelerate DLMS/COSEM security operations, reducing CPU load by >90% vs. software AES. |
| 24-bit ΔΣ A/D Converter | 3-channel high-resolution sampling at 24-bit depth enables Class 0.2 metering accuracy without external sigma-delta modulators. |
| Ultra-Low Power Operation | Halt mode current < 0.5 µA (typ.) with RTC active; extends battery life beyond 10 years in AMI endpoint deployments. |
| On-Chip Data Flash | 2 KB with 1M rewrite cycles and background operation; stores tariff tables, firmware patches, and event logs without halting application code. |
| Peripheral I/O Redirection | PIOR0 register enables dynamic pin function remapping; simplifies PCB layout reuse across meter variants with differing sensor interfaces. |
Applications
| Smart Electricity Meter | AMI Communication Module |
|---|---|
|
Use Scenario: Residential and commercial smart meters performing real-time energy measurement, tariff switching, and tamper detection. IC Role / Device Role / Timing Role: Primary metrology controller executing DLMS/COSEM stack, managing ΔΣ ADC sampling, RTC-based billing intervals, and AES-secured data uploads. Use Value: Integrated 24-bit ΔΣ ADC and hardware AES eliminate need for external metrology ICs and crypto accelerators, reducing BOM cost by ~$1.20/unit. |
Use Scenario: PLC, RF, or optical communication modules interfacing with host meters to relay consumption data to utility headends. IC Role / Device Role / Timing Role: Protocol gateway handling physical layer framing, CRC generation, and secure payload encryption before transmission. Use Value: Dual UARTs (including LIN-capable UART2) and ELC-driven event linking enable deterministic response to PLC carrier detect or RF packet arrival within 1.2 µs. |
| Prepayment Meter Controller | Grid Edge Sensor Node |
|
Use Scenario: Pay-as-you-go meters requiring secure credit validation, local energy accounting, and display-driven user interaction. IC Role / Device Role / Timing Role: Secure transaction processor managing AES-encrypted token validation, EEPROM-backed credit ledger, and LCD/keypad interface. Use Value: On-chip data flash with 1M rewrite cycles ensures >15-year ledger durability; integrated buzzer outputs drive audible credit alerts without external drivers. |
Use Scenario: Distribution transformer monitoring units measuring voltage sag/swell, harmonic distortion, and neutral current imbalance. IC Role / Device Role / Timing Role: High-precision analog front-end controller synchronizing 24-bit ΔΣ ADC sampling with 32.768 kHz RTC for time-aligned waveform capture. Use Value: Independent VRTC supply and dedicated RTCOUT pin enable sub-second timestamping of events for IEEE 1159-compliant power quality logging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F10NMJDFB#35 | 256 KB code flash, 16 KB RAM, same 80-pin LFQFP package and peripheral set; adds 1 MB address space support. | Required for larger DLMS/COSEM implementations with multiple tariff zones, firmware OTA, and extended event logging buffers. | Select when future-proofing for advanced AMI features or migrating legacy 128 KB designs to higher memory headroom. |
| R5F10NPGDFB#35 | 100-pin LFQFP, 128 KB flash, 8 KB RAM, adds UART3/I²C3/CSI3 and 6-channel 10-bit ADC; no hardware AES. | Suitable for non-secure grid sensors or auxiliary metering modules where crypto is handled externally or omitted. | Choose when additional serial interfaces or analog inputs are needed and AES is not mandated by utility security policy. |
Compared with R5F10NMGDFB#35, R5F10NMJDFB#35 offers scalable memory for evolving AMI firmware, while R5F10NPGDFB#35 trades AES for expanded I/O and analog resources - enabling cost-optimized variants without compromising metrology precision.
Availability
R5F10NMGDFB#35 is available at Aetrix Electronics and suitable for smart electricity metering, AMI communication modules, prepayment meter controllers, and grid edge sensor nodes requiring stable component supply across long-lifecycle utility programs.
Supply support for R5F10NMGDFB#35 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RL78/I1C product line is engineered specifically for ultra-low-power, high-accuracy electricity metering applications - integrating metrology-grade ADCs, secure crypto engines, and RTC functionality into a single chip.
FAQ
What is the maximum operating frequency of the R5F10NMGDFB#35?
The R5F10NMGDFB#35 supports a maximum CPU clock of 32 MHz via its integrated PLL. This frequency is achievable with VDD = 2.8 V to 5.5 V and enables minimum instruction execution time of 0.03125 µs - critical for real-time metrology calculations and fast DLMS/COSEM response in the R5F10NMGDFB#35.
Does the R5F10NMGDFB#35 include hardware AES acceleration?
Yes, the R5F10NMGDFB#35 includes a dedicated on-chip AES circuit supporting GCM, ECB, and CBC cipher modes with 128-, 192-, and 256-bit key lengths. This hardware engine is confirmed in Renesas documentation (R01DS0281EJ0231, Note 7 and Table 1-1) and eliminates software-based crypto bottlenecks in the R5F10NMGDFB#35.
How many channels does the ΔΣ A/D converter have in the R5F10NMGDFB#35?
The R5F10NMGDFB#35 integrates a 24-bit ΔΣ A/D converter with three input channels, as specified for 80-pin RL78/I1C devices in Section 1.5.2 and Table 1-1 of the R01DS0281EJ0231 datasheet - distinct from the four-channel version in 100-pin variants.
What is the package type and pin count of the R5F10NMGDFB#35?
The R5F10NMGDFB#35 uses an 80-pin plastic LFQFP package (12 × 12 mm, 0.5 mm pitch), designated "FB" in the part number and confirmed in Table 1-1 and Section 1.3.2 of the R01DS0281EJ0231 datasheet - matching the physical layout and thermal profile required for R5F10NMGDFB#35 deployment in sealed meter enclosures.
What low-power modes are supported by the R5F10NMGDFB#35?
The R5F10NMGDFB#35 supports HALT, STOP, and SNOOZE modes. In STOP mode with RTC active, typical current consumption is less than 0.5 µA (R01DS0281EJ0231, Section 1.1), enabling decade-long battery backup for timekeeping - a core requirement for R5F10NMGDFB#35 in AMI endpoint applications.
R5F10NMGDFB#35 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 80-LQFP
- Series:
- RL78/I1C
- Packaging:
- Tray
- Product Status:
- Last Time Buy
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 24MHz
- Connectivity:
- CSI, I2C, IrDA, LINbus, UART/USART
- Peripherals:
- LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 44
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 2K x 8
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 5.5V
- Data Converters:
- A/D 4x10b, 3x24b Sigma-Delta
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F10NMGDFB#35 FAQ
1.How can I place an order for R5F10NMGDFB#35 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F10NMGDFB#35 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F10NMGDFB#35 reliable?
The price and inventory of R5F10NMGDFB#35 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F10NMGDFB#35 is usually 5 days.
3.What payment methods are accepted for R5F10NMGDFB#35?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F10NMGDFB#35 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F10NMGDFB#35?
R5F10NMGDFB#35 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F10NMGDFB#35 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F10NMGDFB#35?
For technical support, including R5F10NMGDFB#35 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F10NMGDFB#35 requirements.
6.How does Aetrix verify that R5F10NMGDFB#35 is sourced from the original manufacturer or authorized distributors?
All R5F10NMGDFB#35 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F10NMGDFB#35 meets industry standards.
7.What is the process for return or replacement of R5F10NMGDFB#35?
All R5F10NMGDFB#35 units undergo pre-shipment inspection (PSI). If there is an issue with R5F10NMGDFB#35, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F10NMGDFB#35 part is unused and in its original packaging.
Return procedure for R5F10NMGDFB#35:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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