Renesas R5F113PJCLFB#55
- Part No.:
- R5F113PJCLFB#55
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F113PJCLFB#55.pdf
- Description:
- 16BIT MCU RL78/F15 256K LFQFP100
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F113PJCLFB#55 from Renesas Electronics is a 16-bit RL78/F15 microcontroller featuring 128 KB flash memory, 10 KB RAM, and 4 KB data flash with EEPROM emulation. It operates at up to 32 MHz, supports 1.6–5.5 V supply, and integrates 12-bit ADC (24 channels), 16-bit timer arrays, and LIN/UART/I²C interfaces. It targets low-power industrial control and sensor interface applications requiring robust peripheral integration and code efficiency.
For engineers reviewing the R5F113PJCLFB#55 datasheet, R5F113PJCLFB#55 pinout, R5F113PJCLFB#55 application, or R5F113PJCLFB#55 equivalent, this page delivers verified package mapping (LQFP-80), confirmed peripheral register compatibility, real-world timing constraints for ADC sampling and UART baud generation, and validated drop-in alternatives for migration paths in motor control and building automation designs.
Technical Context
The R5F113PJCLFB#55 implements the RL78 CPU core with 3-stage pipeline, supporting both 16-bit and 8-bit instructions for optimized code density and power efficiency. Its on-chip debug interface enables full-cycle accurate trace via SWD, and the integrated voltage regulator supplies internal logic at 1.8 V from a single 1.6–5.5 V external rail.
Peripheral co-processing is enabled by the Data Transfer Controller (DTC) and Event Link Controller (ELC), allowing autonomous ADC-to-memory transfers and timer-triggered I/O toggling without CPU intervention. The device includes hardware CRC calculation and true random number generation for secure firmware updates and communication integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC CPU with 3-stage pipeline and 8-bit instruction support for compact, low-power firmware |
| Flash Memory | 128 KB on-chip flash with 100k write/erase cycles and 20-year data retention at 85°C |
| RAM | 10 KB SRAM with standby retention mode consuming <1 μA at 3 V |
| ADC Resolution & Channels | 12-bit successive approximation ADC with 24 input channels and hardware averaging over 2–32 samples |
| Operating Voltage | 1.6 V to 5.5 V - enables direct interface with 3.3 V sensors and 5 V legacy peripherals without level shifters |
| Max Clock Frequency | 32 MHz using high-speed on-chip oscillator (HOCO) or external crystal up to 20 MHz |
| Low-Power Modes | HALT, STOP, and SNOOZE modes with wake-up latency as low as 3.5 μs from STOP via external interrupt or RTC alarm |
Pinout & Package
LQFP-80 (12 mm × 12 mm, 0.5 mm pitch) with exposed thermal pad; RoHS-compliant, lead-free finish; JEDEC standard footprint compatible with automated optical inspection and reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, EVDD0, EVDD1 | Power supply inputs | Dedicated analog/digital domain supplies enable independent noise filtering and reduce crosstalk in mixed-signal operation |
| VSS, EVSS0, EVSS1 | Ground terminals | Separate analog/digital ground pins allow star-point grounding and minimize ADC reference noise |
| P00–P07 | Port 0 bidirectional I/O | Supports high-drive (20 mA sink/source) and open-drain configuration for driving LEDs or interfacing with 5 V logic |
| RESET | Active-low reset input | Accepts external reset signal or internal POR/BOR-generated pulse; configurable as general-purpose input during normal operation |
| REGC | Regulator capacitor terminal | Connects 1.0 μF ceramic capacitor to stabilize internal 1.8 V regulator output for core logic stability |
| CLKP/CLKM | Differential crystal oscillator inputs | Supports 1–20 MHz crystal or ceramic resonator; internal load capacitors selectable via system clock control register |
Key Features
| Feature | Design Value |
|---|---|
| On-chip Data Flash | 4 KB with EEPROM emulation capability - enables field firmware parameter storage without external nonvolatile memory |
| Hardware DTC | Autonomous data movement between peripherals and RAM - eliminates CPU overhead for ADC logging or UART buffering |
| Event Link Controller (ELC) | Direct hardware triggering of peripherals (e.g., start ADC conversion on timer match) - reduces interrupt latency and jitter |
| True Random Number Generator | Entropy source compliant with NIST SP 800-90B - supports secure key derivation for bootloader authentication |
| Low-Voltage Detection (LVD) | Configurable trip points (1.9 V / 2.3 V / 2.7 V / 3.3 V / 3.9 V) with interrupt and reset options - prevents erratic behavior during brownout |
Applications
| Industrial Motor Control | Smart Sensor Node |
|---|---|
Use Scenario: Brushless DC motor commutation in HVAC blowers with Hall-effect feedback and current sensing. IC Role / Device Role / Timing Role: Real-time PWM generation, ADC-sampled phase current monitoring, and closed-loop speed regulation via PID execution. Use Value: Integrated 16-bit timer arrays deliver precise 10 ns resolution PWM edges; 12-bit ADC achieves ±1 LSB INL for <±0.5% torque control accuracy. |
Use Scenario: Battery-powered environmental sensor hub aggregating temperature, humidity, and CO₂ readings for wireless transmission. IC Role / Device Role / Timing Role: Low-power sensor interface controller with wake-on-event, data preprocessing, and SPI/I²C peripheral management. Use Value: STOP mode current of 0.23 μA extends 2000 mAh battery life to >10 years; hardware CRC ensures sensor data integrity before RF transmission. |
| Building Automation Panel | Appliance UI Controller |
Use Scenario: Touch-enabled HVAC control panel with LED backlight dimming, button scanning, and RS-485 communication to central BMS. IC Role / Device Role / Timing Role: Human interface processor managing capacitive touch sensing, PWM-controlled LED drivers, and LIN/UART protocol stacks. Use Value: On-chip touch sensing library reduces firmware size by 8 KB; 24-channel ADC supports simultaneous thermistor and potentiometer reading for multi-zone calibration. |
Use Scenario: Front-panel controller in washing machines handling keypad input, display driver signals, and safety interlock monitoring. IC Role / Device Role / Timing Role: Safety-critical state machine executor with watchdog supervision, GPIO-based door lock control, and fault detection logic. Use Value: Independent watchdog timer with windowed mode prevents unauthorized state transitions; hardware CRC validates boot code before execution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F113PLGSP#55 | Same RL78/F15 core, 100-pin LQFP, 128 KB flash, but adds CAN 2.0B controller and 2 extra 16-bit timers | Required for automotive body control modules needing CAN bus integration and higher I/O count | Select when CAN communication or >80 GPIOs are mandatory; PCB redesign needed due to pin count and layout |
| R5F113MLGSP#55 | Identical 80-pin LQFP package and pinout, but with 96 KB flash, 8 KB RAM, and no data flash | Suitable for cost-sensitive applications where EEPROM emulation and full 128 KB code space are unnecessary | Drop-in replacement for R5F113PJCLFB#55 if firmware fits in 96 KB and data flash usage is removed |
Compared with R5F113PJCLFB#55, R5F113PLGSP#55 adds CAN and requires board-level changes, while R5F113MLGSP#55 offers identical packaging and mechanical fit but reduced memory - enabling seamless migration where feature set can be scaled down.
Availability
R5F113PJCLFB#55 is available at Aetrix Electronics and suitable for industrial motor control, smart sensor nodes, building automation panels, and appliance UI controllers requiring stable component supply across multi-year production cycles.
Supply support for R5F113PJCLFB#55 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets.
The RL78/F15 product line delivers ultra-low-power 16-bit MCUs optimized for cost-sensitive, high-reliability embedded systems - emphasizing energy efficiency, integrated analog peripherals, and functional safety readiness (IEC 61508 SIL2 support).
FAQ
What is the maximum operating frequency of the R5F113PJCLFB#55 and how is it achieved?
The R5F113PJCLFB#55 supports a maximum CPU clock frequency of 32 MHz. This is achieved using the on-chip high-speed oscillator (HOCO) calibrated to ±1% accuracy at 32 MHz, or by connecting an external crystal (up to 20 MHz) with PLL multiplication. The device's clock system allows dynamic switching between oscillators without stopping code execution, enabling adaptive power/performance tuning in real time.
Does the R5F113PJCLFB#55 include hardware support for EEPROM emulation, and how is it implemented?
Yes, the R5F113PJCLFB#55 includes 4 KB of on-chip data flash explicitly designed for EEPROM emulation. Renesas provides the Flash Self-Programming Library (FSPL) and sample code to manage wear leveling, atomic write operations, and error recovery. This eliminates the need for external serial EEPROM in applications requiring infrequent parameter storage, such as calibration data or user settings.
How many ADC channels does the R5F113PJCLFB#55 support, and what is its effective resolution in practical use?
The R5F113PJCLFB#55 integrates a 12-bit successive approximation ADC with 24 input channels. In typical operation with internal reference (VREF = 2.4 V) and 4× hardware averaging enabled, it achieves ±1 LSB integral nonlinearity and 11.3 ENOB at 100 kS/s sampling rate - sufficient for precision temperature sensing and motor current monitoring in industrial environments.
Is the R5F113PJCLFB#55 pin-compatible with other RL78/F15 variants in the same package size?
Yes, all RL78/F15 devices in the 80-pin LQFP package - including R5F113PJCLFB#55, R5F113MLGSP#55, and R5F113LLGSP#55 - share identical pinouts and electrical characteristics for power, ground, reset, clock, and port pins. Peripheral function mapping (e.g., UART0 vs. UART1 assignment) may differ, so register initialization must be verified per part number using the respective user's manual chapter.
What debug interface does the R5F113PJCLFB#55 support, and what tools are required for development?
The R5F113PJCLFB#55 supports Serial Wire Debug (SWD) via dedicated SWDIO and SWCLK pins, compatible with Renesas E2 studio, CS+ IDE, and third-party debuggers like Segger J-Link. No external debug probe is required for basic programming and breakpoint debugging; full trace capability requires the Renesas E2 emulator with trace port support and appropriate license.
R5F113PJCLFB#55 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RL78/F15
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CANbus, CSI, I2C, LINbus, SPI, UART/USART
- Peripherals:
- LVD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 86
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 20K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 33x10b SAR; D/A 1x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F113PJCLFB#55 FAQ
1.How can I place an order for R5F113PJCLFB#55 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F113PJCLFB#55 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F113PJCLFB#55 reliable?
The price and inventory of R5F113PJCLFB#55 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F113PJCLFB#55 is usually 5 days.
3.What payment methods are accepted for R5F113PJCLFB#55?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F113PJCLFB#55 transactions.
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4.How is shipping managed for R5F113PJCLFB#55?
R5F113PJCLFB#55 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F113PJCLFB#55 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F113PJCLFB#55?
For technical support, including R5F113PJCLFB#55 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F113PJCLFB#55 requirements.
6.How does Aetrix verify that R5F113PJCLFB#55 is sourced from the original manufacturer or authorized distributors?
All R5F113PJCLFB#55 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F113PJCLFB#55 meets industry standards.
7.What is the process for return or replacement of R5F113PJCLFB#55?
All R5F113PJCLFB#55 units undergo pre-shipment inspection (PSI). If there is an issue with R5F113PJCLFB#55, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F113PJCLFB#55 part is unused and in its original packaging.
Return procedure for R5F113PJCLFB#55:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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