Renesas R5F11Y67ASM#30
- Part No.:
- R5F11Y67ASM#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
R5F11Y67ASM#30.pdf
- Description:
- IC MCU 16BIT 4KB FLASH 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,400
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Product details
Overview
R5F11Y67ASM#30 from Renesas Electronics is an ultra-low-power 16-bit RL78/G1N microcontroller in a 20-pin TSSOP package, featuring 4 KB flash memory, 512 B RAM, 8-channel 8/10-bit A/D converter, 1 UART, 1 CSI, 4-channel 16-bit timer, and watchdog timer - deployed in battery-powered consumer sensor nodes requiring compact size and extended runtime.
For engineers reviewing the R5F11Y67ASM#30 datasheet, R5F11Y67ASM#30 pinout, R5F11Y67ASM#30 application, or R5F11Y67ASM#30 equivalent, key selection criteria include its 20-pin TSSOP footprint, 4 KB flash/512 B RAM configuration, -40°C to +85°C industrial temperature grade, VDD = 2.0–5.5 V operation, and RL78/G1N-specific high-current P-ch open-drain I/O capability on P00–P05 pins.
Technical Context
The R5F11Y67ASM#30 implements the RL78 CPU core with CISC architecture and 3-stage pipeline, supporting minimum instruction execution time of 0.05 µs at 20 MHz (high-speed on-chip oscillator) and 1.0 µs at 1 MHz (low-speed mode). It integrates selectable power-on-reset (SPOR) with four detection voltage options (2.25 V to 4.45 V) and operates across VDD = 2.0–5.5 V with mandatory use within 2.25–5.5 V due to SPOR threshold constraints.
This device belongs to the RL78/G1N group (denoted by "Y" in part number), distinguishing it from G1M with enhanced P-ch open-drain output capability on P00–P05 (–120 mA per pin at VDD = 4.5–5.5 V), absence of real-time output (RTIO) channels, and optimized peripheral I/O mapping for segment-com driver applications - confirmed via Pin Configuration (1.3.2) and Function Outline (1.6) in R01DS0378EJ0100 Rev.1.00.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC CPU with 3-stage pipeline; enables deterministic timing control for real-time sensor polling and low-latency interrupt response. |
| Flash / RAM | 4 KB code flash memory and 512 B on-chip RAM; sufficient for compact firmware with sensor interface logic, calibration tables, and UART-based telemetry. |
| Operating Voltage | VDD = 2.0–5.5 V (use range 2.25–5.5 V); supports direct connection to Li-ion, alkaline, or regulated 3.3 V/5 V rails without external LDO overhead. |
| A/D Converter | 8-channel 8/10-bit SAR ADC (VDD = 2.4–5.5 V); allows simultaneous monitoring of thermistor, potentiometer, and supply rail voltages with programmable sampling rate. |
| Timer Resources | Four 16-bit timer channels + 12-bit interval timer + watchdog timer; supports PWM generation, periodic wake-up from HALT/STOP, and system-level fault recovery. |
| I/O Capability | 18 total I/O pins: 14 N-ch open-drain (VDD-tolerant), 6 P-ch open-drain (high-current); enables direct LED/segment driving and robust level-shifting in mixed-voltage systems. |
| Serial Interfaces | 1 UART channel (up to 3.3 Mbps theoretical) + 1 CSI channel (master/slave SPI-compatible); provides reliable host communication and peripheral daisy-chaining without external transceivers. |
Pinout & Package
Package: 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65 mm pitch), RoHS-compliant, tray-packaged (#30 suffix).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00–P05 | P-ch open-drain output / INTP5/INTP4 | High-current sink/source (–120 mA per pin, 4.5–5.5 V); ideal for driving LED segments or relays without external drivers. |
| P06, P07, P10–P16, P40 | N-ch open-drain I/O / analog input / serial interface | VDD-tolerant (14 pins); supports mixed-signal interfacing, level translation, and shared-bus configurations with pull-up resistors. |
| P125 | KR1 / RESET | Active-low reset input with internal pull-up; accepts external reset button or supervisor IC signal for controlled power-up sequencing. |
| P137 | TI00 / INTP0 | External interrupt/timer input; used for zero-crossing detection, encoder quadrature decoding, or wake-on-event functionality. |
| VDD / VSS | Power supply / ground | Dual power pins enable low-impedance decoupling; requires 0.1 µF ceramic capacitor close to VDD pin for stable 20 MHz operation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-power HALT/STOP modes | HALT draws ≤980 µA (20 MHz), STOP draws ≤2.35 µA (VDD = 3 V); extends battery life in intermittent-sensing applications like smart thermostats. |
| Selectible SPOR voltage | Four rising-edge thresholds (2.25/2.68/3.02/4.45 V); ensures reliable reset across wide input voltage ranges in unregulated battery systems. |
| On-chip debug support | Integrated debug interface via TOOL0 pin; enables in-circuit programming and real-time trace without external JTAG adapter. |
| Programmable clock/buzzer output | PCLBUZ0 pin delivers 2.44 kHz–10 MHz square wave; drives piezo buzzers or clocks external logic with no external oscillator required. |
| Peripheral I/O redirection | PIOR register allows dynamic remapping of UART/CSI pins to alternate ports; increases PCB layout flexibility and reduces routing congestion. |
Applications
| Smart Home Sensor Node | Industrial Panel Indicator |
|---|---|
|
Use Scenario: Battery-powered temperature/humidity sensor transmitting data via UART to gateway every 30 seconds. IC Role / Device Role / Timing Role: Main controller executing sensor readout, ADC conversion, UART framing, and deep-sleep management. Use Value: 4 KB flash stores firmware + OTA update buffer; 512 B RAM holds sensor readings and packet buffers; STOP mode current <2.35 µA enables >2-year coin-cell operation. |
Use Scenario: DIN-rail mounted status indicator with 7-segment display and push-button inputs. IC Role / Device Role / Timing Role: Segment driver and key scanner managing multiplexed display and debounce logic. Use Value: P-ch open-drain outputs (P00–P05) drive common-anode segments directly; KR0–KR7 key return inputs eliminate external scan matrix hardware. |
| Portable Medical Monitor | White Goods Control Module |
|
Use Scenario: Handheld pulse oximeter with analog front-end and buzzer feedback. IC Role / Device Role / Timing Role: Signal acquisition controller synchronizing ADC sampling, calculating SpO₂, and generating audible alerts. Use Value: 8-channel ADC interfaces photodiode and reference sensors simultaneously; PCLBUZ0 generates calibrated tone without external driver circuitry. |
Use Scenario: Washing machine main board controlling motor, valves, and user interface. IC Role / Device Role / Timing Role: Secondary MCU handling UI, door lock logic, and fault reporting via UART to main controller. Use Value: 18 GPIOs manage buttons, LEDs, buzzer, and relay drivers; UART enables diagnostics and firmware updates over service port. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F11Y68ASM#30 | 8 KB flash, 1 KB RAM, same package and peripherals; higher memory headroom for feature-rich firmware. | Suitable where bootloader, encryption, or larger calibration tables are required. | Select when future firmware expansion or dual-bank OTA is needed; identical pinout and software compatibility. |
| R5F11W67ASM#30 | RL78/G1M variant: includes RTIO0–RTIO7 outputs, lacks P-ch open-drain capability on P00–P05. | Better suited for real-time waveform generation (e.g., motor commutation) than segment driving. | Choose only if real-time output channels are essential; not drop-in compatible due to functional pin differences. |
Compared with R5F11Y67ASM#30, R5F11Y68ASM#30 offers scalable memory without layout or firmware changes, while R5F11W67ASM#30 trades P-ch I/O strength for real-time output capability - making R5F11Y67ASM#30 optimal for cost-sensitive, high-current digital I/O applications.
Availability
R5F11Y67ASM#30 is available at Aetrix Electronics and suitable for smart home sensor nodes, industrial panel indicators, portable medical monitors, and white goods control modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for R5F11Y67ASM#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The R5F11Y67ASM#30 belongs to the RL78/G1N microcontroller family, designed specifically for cost-sensitive, ultra-low-power consumer and industrial applications demanding high-current digital I/O, integrated analog sensing, and minimal external components.
FAQ
What is the maximum operating frequency and instruction execution time of the R5F11Y67ASM#30?
The R5F11Y67ASM#30 supports a high-speed on-chip oscillator up to 20 MHz, enabling a minimum instruction execution time of 0.05 µs under VDD ≥ 2.7 V. At lower VDD (2.0–2.7 V), the max frequency drops to 5 MHz with 0.2 µs minimum cycle time. The RL78 CPU core uses a 3-stage pipeline to maintain deterministic timing across all operating conditions, and the R5F11Y67ASM#30 maintains full functionality across its specified VDD and temperature range.
Does the R5F11Y67ASM#30 support hardware debugging and in-system programming?
Yes, the R5F11Y67ASM#30 includes an on-chip debug function accessible via the TOOL0 pin, enabling full in-circuit debugging, flash programming, and real-time trace without external JTAG adapters. This capability is documented in Section 1.1 and Section 2.1 of R01DS0378EJ0100 Rev.1.00. However, Renesas advises against using the debug function in mass-produced end products due to flash endurance limitations - the R5F11Y67ASM#30 must be programmed during manufacturing and operated in production mode thereafter.
What are the key differences between R5F11Y67ASM#30 and R5F11W67ASM#30?
The R5F11Y67ASM#30 is an RL78/G1N device with P-ch open-drain outputs on P00–P05 (–120 mA per pin), while R5F11W67ASM#30 is an RL78/G1M device offering real-time output (RTIO0–RTIO7) but lacking high-current P-ch drive. Both share 4 KB flash, 512 B RAM, and 20-pin TSSOP packaging, but their peripheral mappings differ - for example, P16 on R5F11Y67ASM#30 supports TxD0, whereas on R5F11W67ASM#30 it does not. Thus, R5F11Y67ASM#30 is not pin-compatible with R5F11W67ASM#30 for P-ch I/O applications.
Can the R5F11Y67ASM#30 operate from a single 3.0 V lithium coin cell?
Yes, the R5F11Y67ASM#30 operates across VDD = 2.0–5.5 V and is explicitly rated for 3.0 V operation in HALT and STOP modes, drawing as little as 300 µA (HALT) and 0.61 µA (STOP, typical at 25°C). Its selectable SPOR circuit includes a 2.25 V threshold option, ensuring reliable reset as the coin cell discharges below 2.5 V. The R5F11Y67ASM#30 also supports low-voltage ADC operation down to VDD = 2.4 V, making it suitable for long-life battery-powered designs.
What serial interface protocols does the R5F11Y67ASM#30 support?
The R5F11Y67ASM#30 integrates one UART channel (supporting asynchronous communication up to 3.3 Mbps theoretical rate at 20 MHz) and one CSI channel configurable as SPI master or slave. The UART supports standard framing (start/stop bits, parity), while CSI supports clock polarity/phase control (CKP/DAP bits) and variable SCK timing for interoperability with diverse peripherals. Neither interface requires external level shifters or protocol accelerators - the R5F11Y67ASM#30 handles all framing, clock generation, and data buffering in hardware.
R5F11Y67ASM#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Series:
- RL78/G1N
- Packaging:
- Tray
- Product Status:
- Last Time Buy
- Programmable:
- -
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 20MHz
- Connectivity:
- CSI, UART/USART
- Peripherals:
- POR, WDT
- Number of I/O:
- 16
- Program Memory Size:
- 4KB (4K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512 x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 5.5V
- Data Converters:
- A/D 8x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F11Y67ASM#30 FAQ
1.How can I place an order for R5F11Y67ASM#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F11Y67ASM#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F11Y67ASM#30 reliable?
The price and inventory of R5F11Y67ASM#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F11Y67ASM#30 is usually 5 days.
3.What payment methods are accepted for R5F11Y67ASM#30?
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R5F11Y67ASM#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F11Y67ASM#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F11Y67ASM#30?
For technical support, including R5F11Y67ASM#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F11Y67ASM#30 requirements.
6.How does Aetrix verify that R5F11Y67ASM#30 is sourced from the original manufacturer or authorized distributors?
All R5F11Y67ASM#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F11Y67ASM#30 meets industry standards.
7.What is the process for return or replacement of R5F11Y67ASM#30?
All R5F11Y67ASM#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F11Y67ASM#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F11Y67ASM#30 part is unused and in its original packaging.
Return procedure for R5F11Y67ASM#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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