Renesas R5F21355CDFP#V2
- Part No.:
- R5F21355CDFP#V2
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 52-LQFP
- Datasheet:
-
R5F21355CDFP#V2.pdf
- Description:
- IC MCU 16BIT 24KB FLASH 52LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,955
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F21355CDFP#V2 from Renesas Electronics is a 16-bit R8C CPU core MCU with 24 KB flash program ROM, 2 KB data flash (4 × 1 KB blocks), and 2 KB RAM, operating at up to 20 MHz (VCC = 2.7–5.5 V) with 50 ns minimum instruction execution time; it integrates UART0/1/2, I²C, LIN, 12-channel 10-bit ADC, dual 8-bit DAC, and six timer modules (RA–RE + RD dual 16-bit), targeting embedded control in consumer audio and office equipment.
For engineers reviewing the R5F21355CDFP#V2 datasheet, R5F21355CDFP#V2 pinout, R5F21355CDFP#V2 application, or R5F21355CDFP#V2 equivalent, key selection criteria include its -40°C to +85°C industrial temperature grade, 52-pin LQFP package with 47 CMOS I/O ports, background operation (BGO) for data flash, and hardware LIN module using Timer RA and UART0.
Technical Context
The R5F21355CDFP#V2 implements the R8C CPU core with 89 fundamental instructions, 16×16→32-bit multiplier, and multiply-accumulate capability. Its memory map spans 1 Mbyte (00000h–FFFFFh), with program ROM starting at 0A000h and data flash at 03000h–03FFFh.
It supports four clock sources: XIN (up to 20 MHz), XCIN (32 kHz), high-speed on-chip oscillator (adjustable), and low-speed on-chip oscillator. Power management includes wait mode (3.5 µA @ 3.0 V, f(XCIN)=32 kHz) and stop mode (2.0 µA @ 3.0 V), with voltage detection circuits for power-on reset and configurable level monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | R8C 16-bit core with 89 instructions, 50 ns min. instruction time at 20 MHz |
| Memory | 24 KB flash program ROM, 2 KB RAM, 4 × 1 KB data flash blocks with BGO |
| Operating Temp | -40°C to +85°C (D version), enabling industrial-grade reliability |
| Peripherals | UART0/1/2, I²C bus, hardware LIN, 12-channel 10-bit ADC, dual 8-bit DAC |
| Timers | Timer RA (8-bit), RB (8-bit), RC (16-bit), RD (dual 16-bit), RE (8-bit real-time clock) |
| Power Modes | Standard, wait (3.5 µA), and stop (2.0 µA) modes with selectable oscillators |
| Package | 52-pin LQFP (PLQP0052JA-A), 10 mm × 10 mm, 0.65 mm pitch |
Pinout & Package
52-pin LQFP package (PLQP0052JA-A), 10 mm × 10 mm body, 0.65 mm pin pitch, with exposed thermal pad not electrically connected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0_0–P0_7 | CMOS I/O port with analog input (AN0–AN7) | Configurable as digital I/O or ADC inputs; P0_6/P0_7 support DA0/DA1 outputs |
| P1_0–P1_7 | CMOS I/O port with key interrupt (KI0–KI3) and analog input (AN8–AN11) | Supports wake-up from stop mode via key press; AN8–AN11 feed 10-bit ADC |
| P2_0–P2_7 | CMOS I/O port with TRDIOx timer functions | Primary interface for Timer RD's 6-pin PWM outputs and three-phase waveform generation |
| P3_0–P3_7 | CMOS I/O port with I²C (SCL/SDA), SSU (SSCK/SSI/SSO), and UART2 signals | Shared pins enable flexible peripheral routing; SCL/SDA support standard I²C timing |
| P4_2–P4_7 | VREF input, MODE, RESET, XCIN/XCOUT, XIN/XOUT | VREF sets ADC/DAC reference; MODE selects boot mode; RESET is active-low asynchronous reset |
| P5_6/P5_7 | TRAO output and general-purpose I/O | Timer RA output pin; supports pulse generation and event triggering |
| P6_0–P6_7 | TREO output, INT2/INT3/INT4, UART1/UART2, CLK1/CLK2 | TREO provides divided clock output; P6_3/P6_4 route UART1 TX/RX; P6_5/P6_6 support UART2/SDA2/SCL2 |
Key Features
| Feature | Design Value |
|---|---|
| Background Operation (BGO) | Enables concurrent program execution and data flash erase/write without halting CPU |
| Hardware LIN Module | Integrated LIN 2.0/2.1 support via Timer RA and UART0, eliminating external transceiver need |
| Dual 8-bit D/A Converters | Provides independent analog outputs (DA0/DA1) for audio biasing or sensor calibration |
| 12-Channel 10-bit ADC with Sweep Mode | Automatically sequences all 12 analog inputs for rapid system monitoring without software overhead |
| Low-Power Stop Mode (2.0 µA) | Retains RAM content and enables wake-up via INT0–INT4 or key inputs for battery-critical designs |
| Four Independent Clock Sources | Allows dynamic switching between XIN (high speed), XCIN (RTC), and two on-chip oscillators for optimal power/performance trade-off |
Applications
| Audio Equipment Control | Office Equipment Motor Control |
|---|---|
Use Scenario: Volume, tone, and source selection logic in portable audio systems with analog front-end. IC Role / Device Role / Timing Role: Main controller executing user interface firmware, managing ADC readings from potentiometers, and driving DACs for headphone amplification bias. Use Value: Integrated 10-bit ADC and dual 8-bit DAC eliminate external converters; LIN module enables communication with remote displays or sensors. | Use Scenario: Precision speed and position control of paper feed and scanning motors in multifunction printers. IC Role / Device Role / Timing Role: Real-time motor controller generating complementary PWM waveforms via Timer RD for three-phase BLDC drive. Use Value: Timer RD's complementary PWM mode with triangular wave modulation delivers precise phase-shifted outputs on six pins, reducing external gate driver count. |
| Consumer Appliance UI | Industrial Sensor Hub |
Use Scenario: Keypad scanning, display backlight dimming, and temperature monitoring in microwave ovens or washing machines. IC Role / Device Role / Timing Role: System manager handling key input interrupts (KI0–KI3), driving LED segments via high-current I/O ports, and reading thermistor ADC values. Use Value: 47 high-current drive ports simplify LED direct-drive; key interrupt circuitry supports debounce-free wake-up from low-power stop mode. | Use Scenario: Aggregating analog sensor data (voltage, current, temp) and transmitting over UART/I²C to a central gateway. IC Role / Device Role / Timing Role: Data acquisition node performing synchronized 12-channel ADC sweeps and buffering results in 2 KB RAM before transmission. Use Value: ADC sweep mode with sample-and-hold ensures accurate simultaneous sampling across channels; UART2 supports multiprocessor communication for daisy-chained nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F21355CNFP | Same core, peripherals, and memory; rated for -20°C to +85°C (N version) | Suitable for commercial indoor environments only | Select when operating ambient stays above -20°C and cost sensitivity outweighs industrial temp margin |
| R5F21356CDFP | 32 KB program ROM, 2.5 KB RAM, identical peripherals and package | Required for larger firmware images or extended data buffering needs | Choose when application code size exceeds 24 KB or additional RAM is needed for communication stacks |
Compared with R5F21355CNFP, the R5F21355CDFP#V2 offers extended temperature range for harsh environments; compared with R5F21356CDFP, it trades ROM/RAM capacity for lower cost and footprint in resource-constrained designs.
Availability
R5F21355CDFP#V2 is available at Aetrix Electronics and suitable for audio equipment control, office equipment motor control, consumer appliance UI, and industrial sensor hub applications requiring stable component supply across extended temperature ranges.
Supply support for R5F21355CDFP#V2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The R8C/35C Group, including R5F21355CDFP#V2, was designed for cost-sensitive, low-power embedded control in consumer electronics-emphasizing integration of timers, communication interfaces, and mixed-signal peripherals in compact LQFP packages.
FAQ
What is the maximum operating frequency and supply voltage range for the R5F21355CDFP#V2?
The R5F21355CDFP#V2 operates at up to 20 MHz when supplied at 2.7–5.5 V, achieving a minimum instruction execution time of 50 ns. At reduced voltage (1.8–5.5 V), it supports 5 MHz operation with 200 ns minimum instruction time. Its industrial-grade D version guarantees full functionality across -40°C to +85°C ambient temperatures, making R5F21355CDFP#V2 suitable for demanding environmental conditions.
Does the R5F21355CDFP#V2 support in-system programming and debug interfaces?
Yes, the R5F21355CDFP#V2 includes on-chip debug capability and supports in-system flash rewriting via dedicated debug pins. It features ROM code protection and ID code checking for secure firmware deployment. The device uses the standard Renesas E8/E8a debug interface, allowing full breakpoint, step-through, and memory inspection during development-no external programmer is required for basic debugging of R5F21355CDFP#V2 applications.
How does the data flash architecture of the R5F21355CDFP#V2 support firmware updates?
The R5F21355CDFP#V2 contains 4 × 1 KB data flash blocks (total 4 KB) with background operation (BGO) support, enabling concurrent CPU execution and flash erase/write. This allows safe over-the-air or field firmware updates without halting real-time tasks. Each block endures 10,000 write/erase cycles, and BGO eliminates interrupt latency spikes during flash operations-critical for maintaining deterministic timing in R5F21355CDFP#V2-based control systems.
Can the R5F21355CDFP#V2 generate three-phase PWM waveforms for motor control?
Yes, the R5F21355CDFP#V2's Timer RD module supports reset synchronous PWM and complementary PWM modes, directly generating three-phase waveforms on six output pins (TRDIOA0–TRDIOC1). These modes provide synchronized dead-time insertion, sawtooth/triangular wave modulation, and automatic phase shifting-enabling direct drive of three-phase BLDC or stepper motor gate drivers without external logic, a key capability of the R5F21355CDFP#V2 in motion control applications.
What communication interfaces are integrated into the R5F21355CDFP#V2?
The R5F21355CDFP#V2 integrates UART0, UART1, and UART2 (with I²C-bus and multiprocessor modes), one I²C bus (shared with SSU), one synchronous serial unit (SSU), and a dedicated hardware LIN module. UART2 supports full-duplex I²C communication and multiprocessor addressing, while the LIN module uses Timer RA and UART0 to implement LIN 2.0/2.1 protocol-providing robust, low-cost networking for R5F21355CDFP#V2 in distributed sensor and actuator systems.
R5F21355CDFP#V2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 52-LQFP
- Series:
- R8C/3x/35C
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- R8C
- Core Size:
- 16-Bit
- Speed:
- 20MHz
- Connectivity:
- I2C, LINbus, SIO, SSU, UART/USART
- Peripherals:
- POR, PWM, Voltage Detect, WDT
- Number of I/O:
- 47
- Program Memory Size:
- 24KB (24K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 5.5V
- Data Converters:
- A/D 12x10b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F21355CDFP#V2 FAQ
1.How can I place an order for R5F21355CDFP#V2 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F21355CDFP#V2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F21355CDFP#V2 reliable?
The price and inventory of R5F21355CDFP#V2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F21355CDFP#V2 is usually 5 days.
3.What payment methods are accepted for R5F21355CDFP#V2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F21355CDFP#V2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F21355CDFP#V2?
R5F21355CDFP#V2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F21355CDFP#V2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F21355CDFP#V2?
For technical support, including R5F21355CDFP#V2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F21355CDFP#V2 requirements.
6.How does Aetrix verify that R5F21355CDFP#V2 is sourced from the original manufacturer or authorized distributors?
All R5F21355CDFP#V2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F21355CDFP#V2 meets industry standards.
7.What is the process for return or replacement of R5F21355CDFP#V2?
All R5F21355CDFP#V2 units undergo pre-shipment inspection (PSI). If there is an issue with R5F21355CDFP#V2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F21355CDFP#V2 part is unused and in its original packaging.
Return procedure for R5F21355CDFP#V2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F21355CDFP#V2 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

