Renesas R5F51113AGFK#5A
- Part No.:
- R5F51113AGFK#5A
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F51113AGFK#5A.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,000
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Product details
Overview
R5F51113AGFK#5A from Renesas is a 32-bit RX CPU-based microcontroller operating at up to 32 MHz (50 DMIPS), featuring 64 KB on-chip flash, 10 KB SRAM, 8 KB data flash, USB 2.0 full-speed host/function/OTG, 12-bit A/D converter (14 channels), 8-bit D/A converter (2 channels), RTC, and operation from 1.8–3.6 V across −40 to +105°C - deployed in industrial HMI, sensor gateway, and USB-connected embedded control systems.
For engineers reviewing the R5F51113AGFK#5A datasheet, R5F51113AGFK#5A pinout, R5F51113AGFK#5A application, or R5F51113AGFK#5A equivalent, this page delivers verified specifications, package mapping to PLQP0064GA-A (14 × 14 mm, 0.8 mm pitch), functional pin roles, real-world use cases, and two confirmed alternative parts with documented technical and application differences.
Technical Context
The R5F51113AGFK#5A implements a CISC Harvard-architecture RX CPU core with five-stage pipeline, variable-length instructions, and 64-bit accumulator for single-cycle 32×32 multiply-accumulate operations. It integrates an Event Link Controller (ELC) enabling direct module-to-module triggering without CPU intervention, and a Data Transfer Controller (DTC) supporting chain transfers triggered by 82 interrupt sources.
Its clock system includes independent PLL, high-speed on-chip oscillator (32 MHz ±1% over −20 to +85°C), sub-clock (32.768 kHz), and dedicated IWDT oscillator (15 kHz), with configurable ICLK/PCLK/FCLK domains. Power management supports software standby mode (0.44 μA) with 4.8 μs wake-up and three low-power modes synchronized to peripheral clock gating.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard architecture with 5-stage pipeline, 73 basic + 9 DSP instructions, 64-bit accumulator |
| Max Operating Frequency | 32 MHz (50 DMIPS); requires VCC ≥ 2.7 V; no wait states for flash/SRAM access |
| Memory | 64 KB flash (1.8 V programmable), 10 KB SRAM, 8 KB data flash (1M erase/write cycles) |
| Analog Peripherals | 12-bit S12AD with 14 channels, 1.0 μs min conversion time; dual 8-bit DA outputs; integrated temperature sensor |
| Communication Interfaces | USB 2.0 full-speed host/function/OTG (12 Mbps), 3× SCI (async/clock-sync/I²C/SPI), 1× RIIC (400 kbps), 1× RSPI (16 Mbps) |
| Timers & Control | 6-channel MTU2 (PWM, input capture, phase counting), 2× CMT, RTC with calendar/leap-year support, IWDT with dedicated 15 kHz oscillator |
| Package & Environment | PLQP0064GA-A (64-pin LQFP, 14 × 14 mm, 0.8 mm pitch); −40 to +105°C operating range (G-grade) |
Pinout & Package
Package: PLQP0064GA-A - 64-pin LQFP, 14 × 14 mm body, 0.8 mm pitch, exposed pad not present, RoHS-compliant Sn finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Main digital power (1.8–3.6 V) and reference ground; decoupling required per layout guidelines |
| VCC_USB / VSS_USB | USB analog power / ground | Isolated 3.3 V domain for USB transceiver; must tie to main VCC/VSS with low-inductance path |
| USB0_DP / USB0_DM | USB differential data pair | Full-speed (12 Mbps) bidirectional D+/D− signals; require 90 Ω differential impedance routing |
| XTAL / EXTAL | Main crystal oscillator terminals | Support external 1–20 MHz crystal; XTAL is output, EXTAL is input; internal oscillator selectable |
| AN000–AN015 | Analog input channels | 14 dedicated pins for 12-bit A/D conversion; AVCC0/AVSS0/VREFH0/VREFL0 define analog domain |
| DA0 / DA1 | Digital-to-analog outputs | Two 8-bit voltage-output DACs (0 V to VCC); available only on 64-pin packages like R5F51113AGFK#5A |
| RES# | Active-low reset input | Asynchronous hardware reset; asserted low resets CPU, peripherals, and internal state machines |
| MD | Mode selection | Configures boot source (flash/USB) at power-on; must be stable before VCC reaches 1.8 V |
Key Features
| Feature | Design Value |
|---|---|
| Background Operation (BGO) | Data flash erase/write executes concurrently with CPU program execution - enables firmware updates without halting real-time tasks |
| Event Link Controller (ELC) | 35 event sources directly trigger 6 MTU2 channels or other peripherals without CPU ISR overhead - critical for deterministic motor control timing |
| USB OTG with BC Support | Single-port USB 2.0 controller supports host, device, and On-The-Go modes with Battery Charging v1.2 detection - eliminates need for external charger IC in portable designs |
| Dual DAC + Temperature Sensor | Integrated 8-bit DA0/DA1 outputs and calibrated TEMPSA channel enable closed-loop thermal compensation and analog waveform generation without external components |
| IEC 60730 Class B Support | On-chip CAC, IWDT, RAM test assist, and clock fail-detection circuitry simplify certification for household appliance safety-critical applications |
Applications
| Industrial HMI Panel | USB Sensor Gateway |
|---|---|
|
Use Scenario: Compact touch-enabled display panel collecting data from Modbus RTU field sensors and uploading via USB mass storage to PC. IC Role / Device Role / Timing Role: Central MCU executing GUI rendering, protocol translation (SCI → USB), and real-time USB enumeration/state management. Use Value: Integrated USB host + 14-channel A/D + 2× DAC enables direct sensor interface and plug-and-play PC connectivity without external PHY or ADC/DAC chips. |
Use Scenario: Battery-powered environmental node aggregating temperature, humidity, and CO₂ readings, then exporting logs via USB stick. IC Role / Device Role / Timing Role: Low-power data concentrator managing sensor polling, RTC-timestamped logging, and USB mass storage class enumeration. Use Value: Software standby current of 0.44 μA and 4.8 μs wake-up allow multi-week battery life while maintaining precise USB session timing via sub-clock RTC. |
| Motor Control Interface | Smart Appliance Controller |
|
Use Scenario: BLDC motor driver board using hall-effect feedback and PWM commutation, with USB-based configuration and diagnostics. IC Role / Device Role / Timing Role: Real-time motor timing controller generating synchronized 6-channel complementary PWM via MTU2, with ELC-triggered A/D sampling. Use Value: Phase counting mode + double-trigger A/D + ELC linkage ensures <1 μs jitter between hall-edge detection and PWM update - meeting IEC 60730 timing safety margins. |
Use Scenario: Washing machine main control unit performing cycle sequencing, water heating, drum motion, and fault logging with self-test capability. IC Role / Device Role / Timing Role: Safety-certifiable system controller executing IEC 60730 diagnostic routines, monitoring LVD thresholds, and managing watchdog supervision. Use Value: On-chip CAC, dual LVD circuits, IWDT with dedicated oscillator, and RAM test assist reduce external safety component count by ≥40% versus legacy solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F51113AGFM#3A | Same core, memory, and peripherals, but in 64-pin LFQFP (PLQP0064KB-A, 10 × 10 mm, 0.5 mm pitch) | Higher pin density; better suited for space-constrained PCBs where thermal dissipation allows smaller footprint | Select when board area is limited and 0.5 mm pitch assembly capability exists; identical firmware compatibility |
| R5F51113AGFL#3A | Same functionality in 48-pin LFQFP (PLQP0048KB-A, 7 × 7 mm, 0.5 mm pitch); reduced I/O count (30 vs. 46), no D/A, no USB OTG | Targeted at cost-sensitive, lower-peripheral-count applications where USB device-only or no USB suffices | Select for simplified BOM and smaller form factor where DAC, OTG, or >30 GPIOs are unnecessary |
Compared with R5F51113AGFK#5A, the R5F51113AGFM#3A offers identical performance in a smaller 0.5 mm pitch package for tighter layouts, while the R5F51113AGFL#3A trades I/O count, DAC, and OTG capability for lower cost and footprint - enabling scalable design reuse across product tiers.
Availability
R5F51113AGFK#5A is available at Aetrix Electronics and suitable for industrial HMI, USB sensor gateways, and smart appliance controllers requiring stable component supply, long-term lifecycle support, and guaranteed G-grade (−40 to +105°C) operation.
Supply support for R5F5113AGFK#5A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX111 Group, including R5F51113AGFK#5A, was designed for cost-sensitive, USB-connected embedded applications demanding robust real-time performance, integrated analog interfaces, and functional safety support - targeting industrial automation and white goods.
FAQ
What is the maximum operating frequency and voltage requirement for R5F51113AGFK#5A?
The R5F51113AGFK#5A operates at a maximum frequency of 32 MHz, which requires a supply voltage of 2.7–3.6 V. At 1.8–2.4 V, max frequency is 8 MHz; at 2.4–2.7 V, it is 16 MHz. All flash and SRAM accesses are zero-wait-state at full speed, and the high-speed on-chip oscillator achieves ±1% accuracy from −20 to +85°C.
Does R5F51113AGFK#5A support USB On-The-Go (OTG) functionality?
Yes, R5F51113AGFK#5A integrates a USB 2.0 host/function module that fully supports OTG, including ID pin detection (USB0_ID), VBUS sensing (USB0_VBUS), and BC (Battery Charger) v1.2 compliance. The USB0_EXICEN and USB0_VBUSEN pins provide hardware control for OTG power switching and low-power states.
How many analog-to-digital and digital-to-analog channels does R5F51113AGFK#5A include?
R5F51113AGFK#5A includes one 12-bit A/D converter with up to 14 input channels (AN000–AN015), and two 8-bit D/A converters (DA0, DA1). The D/A outputs are available only on 64-pin packages such as R5F51113AGFK#5A - they are omitted in 48-pin and smaller variants.
What low-power modes are supported by R5F51113AGFK#5A, and what is the lowest current draw?
R5F51113AGFK#5A supports three low-power modes: Sleep, Deep Sleep, and Software Standby. In Software Standby mode, supply current drops to 0.44 μA (typical), with wake-up latency of 4.8 μs. This mode retains SRAM content and allows RTC alarm or external pin interrupts to resume operation.
Is R5F51113AGFK#5A qualified for IEC 60730 Class B safety-critical applications?
Yes, R5F51113AGFK#5A includes hardware features required for IEC 60730 Class B compliance: Clock Accuracy Measurement Circuit (CAC), Independent Watchdog Timer (IWDT) with dedicated oscillator, RAM test assist functions, and voltage monitoring with dual LVD circuits - all documented in Renesas' RX111 Functional Safety Manual.
R5F51113AGFK#5A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX111
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 32MHz
- Connectivity:
- I2C, SCI, SPI, USB OTG
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 46
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 10K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 14x12b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F51113AGFK#5A FAQ
1.How can I place an order for R5F51113AGFK#5A through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F51113AGFK#5A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F51113AGFK#5A reliable?
The price and inventory of R5F51113AGFK#5A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F51113AGFK#5A is usually 5 days.
3.What payment methods are accepted for R5F51113AGFK#5A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F51113AGFK#5A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F51113AGFK#5A?
R5F51113AGFK#5A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F51113AGFK#5A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F51113AGFK#5A?
For technical support, including R5F51113AGFK#5A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F51113AGFK#5A requirements.
6.How does Aetrix verify that R5F51113AGFK#5A is sourced from the original manufacturer or authorized distributors?
All R5F51113AGFK#5A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F51113AGFK#5A meets industry standards.
7.What is the process for return or replacement of R5F51113AGFK#5A?
All R5F51113AGFK#5A units undergo pre-shipment inspection (PSI). If there is an issue with R5F51113AGFK#5A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F51113AGFK#5A part is unused and in its original packaging.
Return procedure for R5F51113AGFK#5A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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