Renesas R5F51135ADLJ#20
- Part No.:
- R5F51135ADLJ#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F51135ADLJ#20.pdf
- Description:
- IC MCU 32BIT 128KB FLSH 100TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,365
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F51135ADLJ#20 from Renesas is a 32-bit RX CPU-based microcontroller operating at up to 32 MHz (50 DMIPS), featuring 128 KB on-chip flash, 32 KB SRAM, and 8 KB data flash. It integrates USB 2.0 full-speed host/function/OTG, 12-bit A/D (17 channels), 12-bit D/A (2 channels), RTC, LCD controller (40×4), CTSU (12-channel capacitive touch), and operates from 1.8–3.6 V across –40 to +85°C. It targets embedded human-interface and low-power industrial control applications.
For engineers reviewing the R5F51135ADLJ#20 datasheet, R5F51135ADLJ#20 pinout, R5F51135ADLJ#20 application, or R5F51135ADLJ#20 equivalent, this page delivers verified specifications, package mapping to PTLG0100JA-A (7×7 mm TFLGA), validated peripheral capabilities including USB OTG, CTSU, and RTC, and confirmed alternative options for migration or sourcing continuity.
Technical Context
The R5F51135ADLJ#20 implements the RXv1 core with CISC Harvard architecture, five-stage pipeline, and variable-length instructions enabling ultra-compact code. Its clock system includes high-speed on-chip oscillator (32 MHz ±1%), PLL, sub-clock (32.768 kHz), and dedicated IWDT oscillator (15 kHz), all managed via the Clock Frequency Accuracy Measurement Circuit (CAC).
Peripheral coordination is handled by the Event Link Controller (ELC), which enables direct module-to-module triggering without CPU intervention-e.g., MTU2 generating A/D start triggers-while the Data Transfer Controller (DTC) supports four transfer modes with interrupt-driven chaining. The MCU supports IEC 60730 compliance via built-in RAM test assist, IWDT, and CAC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 5-stage pipeline, 50 DMIPS @ 32 MHz |
| Flash Memory | 128 KB on-chip flash, zero wait states at 32 MHz, programmable at 1.8 V |
| SRAM & Data Flash | 32 KB SRAM (no wait states); 8 KB data flash with 1M erase/write cycles |
| USB Interface | USB 2.0 full-speed (12 Mbps) host/function/OTG with BC (Battery Charger) support |
| Analog Peripherals | 12-bit A/D converter (17 channels, 1.0 µs min conversion); 12-bit D/A (2 channels) |
| Capacitive Touch | CTSU with 12 detection pins, self/mutual capacitance sensing, integrated noise canceller |
| Operating Range | 1.8–3.6 V supply; –40 to +85°C ambient; 3.6 mA typical current @ 32 MHz |
Pinout & Package
Package: PTLG0100JA-A - 100-pin TFLGA, 7 × 7 mm body, 0.65 mm pitch, bottom-side solder balls.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Main digital power domain (1.8–3.6 V); requires local decoupling per datasheet layout guidelines |
| AVCC0 / AVSS0 | Analog power / Analog ground | Independent analog domain for A/D and D/A converters; must be isolated from digital noise |
| USB0_DP / USB0_DM | USB differential data pair | Integrated full-speed transceiver; requires 90 Ω differential impedance routing and ESD protection |
| AN000–AN015, AN021 | A/D input channels | 17 single-ended analog inputs; AN021 supports external trigger (ADTRG0#) for synchronized sampling |
| DA0 / DA1 | D/A output channels | Two independent 12-bit voltage outputs (0.35 V to AVCC – 0.47 V); rail-to-rail capable |
| TS0–TS11 | Capacitive touch sense inputs | 12 dedicated CTSU pins supporting mutual/self-capacitance; require calibrated PCB trace design |
| COM0–COM7 / SEG00–SEG39 | LCD common/segment drivers | Supports 40×4 or 36×8 segment configurations; includes on-chip boost circuit for 5 V panel drive |
Key Features
| Feature | Design Value |
|---|---|
| Event Link Controller (ELC) | Enables 44 event sources to directly trigger peripherals (e.g., MTU→A/D), eliminating CPU overhead and enabling wake-from-standby operation |
| Background Operation (BGO) | Data flash programming/erasing proceeds concurrently with CPU execution-no code stall during firmware updates |
| Low-Power Timer (LPT) | 16-bit timer running from sub-clock or IWDT oscillator during software standby mode (0.44 µA), enabling precise wake-up intervals |
| USB Battery Charging (BC) | Detects D+/D− line states to identify wall adapters, charging ports, or data-only hosts-enabling intelligent power management in portable devices |
| IEC 60730 Support | Includes hardware-assisted RAM test, IWDT, and CAC-reducing software certification burden for Class B safety-critical appliances |
Applications
| Home Appliance Control Panel | Industrial HMI Terminal |
|---|---|
|
Use Scenario: Touch-enabled oven or washing machine interface with real-time status display and parameter adjustment. IC Role / Device Role / Timing Role: R5F51135ADLJ#20 serves as main controller-running CTSU for button detection, LCD driver for segmented display, and RTC for cycle timing. Use Value: Integrated CTSU eliminates external touch IC; 40×4 LCD drive supports multi-segment UI; USB OTG enables field firmware updates via consumer-grade flash drives. |
Use Scenario: Compact, fanless operator terminal in factory automation with serial connectivity and local data logging. IC Role / Device Role / Timing Role: R5F51135ADLJ#20 acts as communication gateway-using SCI/RSPI for PLC interfacing and USB for PC diagnostics. Use Value: Dual 12-bit D/A outputs enable analog setpoint generation; 17-channel A/D monitors sensor inputs; ELC-triggered sampling ensures deterministic response to process events. |
| Portable Medical Device | Smart Energy Meter Interface |
|
Use Scenario: Battery-powered glucose monitor with touch UI, audio feedback, and USB data export. IC Role / Device Role / Timing Role: R5F51135ADLJ#20 manages capacitive touch input, SSI-driven audio codec, and USB mass storage for log file transfer. Use Value: Software standby mode (0.44 µA) extends battery life; integrated temperature sensor calibrates A/D readings; USB BC detects chargers for safe recharging. |
Use Scenario: DIN-rail mounted meter with LCD display, tamper detection, and secure firmware update capability. IC Role / Device Role / Timing Role: R5F51135ADLJ#20 functions as secure UI controller-using CTSU for anti-tamper touch zones and RTC for time-stamped event logging. Use Value: On-chip data flash (8 KB, 1M cycles) stores calibration constants and usage logs; IEC 60730 features simplify functional safety validation; LVD circuits detect brown-out conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F51135ADFP#3A | Same core, memory, and peripherals-but in 100-pin LFQFP (14×14 mm, 0.5 mm pitch) instead of TFLGA | Requires PCB redesign due to larger footprint and different thermal/mechanical mounting | Select when board space allows larger package or when hand-soldering/rework is preferred over fine-pitch BGA |
| R5F51136ADLJ#2A | Upgraded to 256 KB flash and 32 KB SRAM; otherwise identical pinout, package, and peripheral set | Direct drop-in replacement where additional firmware headroom or data buffering is required | Choose for future-proofing or when bootloader, OTA stack, or logging buffers exceed 128 KB flash capacity |
Compared with R5F51135ADLJ#20, R5F51135ADFP#3A offers identical functionality in a larger, more serviceable package but increases board area and thermal resistance, while R5F51136ADLJ#2A provides immediate flash/SRAM scalability without layout changes-making it ideal for incremental feature upgrades.
Availability
R5F51135ADLJ#20 is available at Aetrix Electronics and suitable for home appliance control panels, industrial HMI terminals, portable medical devices, and smart energy meter interfaces requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for R5F51135ADLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX113 Group-including R5F51135ADLJ#20-is designed for cost-sensitive, low-power embedded applications demanding rich analog integration, capacitive touch, USB connectivity, and functional safety support.
FAQ
What is the maximum operating frequency and CPU performance of the R5F51135ADLJ#20?
The R5F51135ADLJ#20 operates at a maximum frequency of 32 MHz and delivers 50 DMIPS (Dhrystone MIPS) performance. This is achieved using the 32-bit RXv1 CPU core with a five-stage pipeline, variable-length instruction set, and on-chip 32-bit multiplier/divider. The R5F51135ADLJ#20 maintains zero wait-state access to both flash and SRAM at full speed, ensuring deterministic real-time execution critical for motor control and HMI responsiveness.
Does the R5F51135ADLJ#20 support USB On-The-Go (OTG) and Battery Charging (BC) detection?
Yes, the R5F51135ADLJ#20 integrates a full-featured USB 2.0 host/function/OTG module compliant with USB 2.0 specification, supporting full-speed (12 Mbps) and low-speed (1.5 Mbps) modes. It includes hardware-level Battery Charging (BC) detection to identify standard downstream ports (SDP), charging downstream ports (CDP), and dedicated chargers (DCP)-enabling intelligent power negotiation without external ICs. The R5F51135ADLJ#20 uses USB0_ID, USB0_VBUS, and USB0_EXICEN pins to manage OTG role switching and VBUS control.
What capacitive touch capabilities does the R5F51135ADLJ#20 provide, and how many channels are supported?
The R5F51135ADLJ#20 includes a dedicated Capacitive Touch Sensing Unit (CTSU) supporting up to 12 detection channels (TS0–TS11) in its 100-pin TFLGA package. It implements both self-capacitance and mutual capacitance sensing methods, with an integrated hardware noise canceller for robust operation in electrically noisy environments. The CTSU operates independently of the CPU, allowing continuous touch scanning during low-power modes. The R5F51135ADLJ#20's CTSU is optimized for button, slider, and proximity applications in consumer and industrial interfaces.
What are the key low-power features of the R5F51135ADLJ#20, and what is its standby current?
The R5F51135ADLJ#20 offers three low-power consumption modes: sleep, deep sleep, and software standby. In software standby mode, it draws only 0.44 µA while maintaining RTC and LPT operation-and recovers in just 4.8 µs. It also features a Low Power Timer (LPT) driven by the sub-clock or IWDT oscillator, enabling precise wake-up intervals without waking the CPU. The R5F51135ADLJ#20 achieves 0.11 mA/MHz in high-speed operating mode, making it suitable for battery-powered and energy-harvesting applications where runtime and responsiveness must coexist.
Is the R5F51135ADLJ#20 qualified for functional safety standards such as IEC 60730?
Yes, the R5F51135ADLJ#20 includes hardware features specifically designed to support IEC 60730 Class B compliance, including a Clock Frequency Accuracy Measurement Circuit (CAC), Independent Watchdog Timer (IWDT) with dedicated 15 kHz oscillator, and built-in functions to assist RAM testing. These reduce software certification effort and enable robust self-test routines for household appliances and industrial controls. The R5F51135ADLJ#20's documentation and reference designs align with Renesas' Functional Safety Package for RX MCUs, providing validated safety mechanisms and failure mode analysis.
R5F51135ADLJ#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX113
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 32MHz
- Connectivity:
- I2C, IrDA, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 80
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 17x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F51135ADLJ#20 FAQ
1.How can I place an order for R5F51135ADLJ#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F51135ADLJ#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F51135ADLJ#20 reliable?
The price and inventory of R5F51135ADLJ#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F51135ADLJ#20 is usually 5 days.
3.What payment methods are accepted for R5F51135ADLJ#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F51135ADLJ#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F51135ADLJ#20?
R5F51135ADLJ#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F51135ADLJ#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F51135ADLJ#20?
For technical support, including R5F51135ADLJ#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F51135ADLJ#20 requirements.
6.How does Aetrix verify that R5F51135ADLJ#20 is sourced from the original manufacturer or authorized distributors?
All R5F51135ADLJ#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F51135ADLJ#20 meets industry standards.
7.What is the process for return or replacement of R5F51135ADLJ#20?
All R5F51135ADLJ#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F51135ADLJ#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F51135ADLJ#20 part is unused and in its original packaging.
Return procedure for R5F51135ADLJ#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F51135ADLJ#20 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

