Renesas R5F51403ADFM#30
- Part No.:
- R5F51403ADFM#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F51403ADFM#30.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:386
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Product details
Overview
R5F51403ADFM#30 from Renesas is a 32-bit RXv2 core MCU operating at up to 48 MHz, featuring 64 KB flash, 16 KB SRAM, 4 KB data flash, 12-bit A/D converter (15 channels), two 8-bit D/A channels, and integrated capacitive touch sensing (32 keys). It supports CAN 2.0B, six SCI channels, I²C, RSPI, RTC, low-power timer, and operates from 1.8–5.5 V in industrial temperature range (–40 to +85°C).
For engineers reviewing the R5F51403ADFM#30 datasheet, R5F51403ADFM#30 pinout, R5F51403ADFM#30 application, or R5F51403ADFM#30 equivalent, this page delivers verified specifications, package mapping (PLQP0064KB-C, 64-pin LFQFP, 10 × 10 mm, 0.5 mm pitch), functional pin roles, real-world use cases, and validated alternative parts for industrial control, HMI, and sensor-edge applications.
Technical Context
The R5F51403ADFM#30 implements the RXv2 CPU core with IEEE-754-compliant 32-bit FPU, 204 CoreMark @ 48 MHz, and on-chip divider (2-cycle latency). Its memory subsystem includes no-wait-state SRAM and flash with 32 MHz ≤ access, plus background operation (BGO) for data flash programming.
Peripherals are orchestrated via Event Link Controller (ELC) - enabling interrupt-free module triggering and linked operation during CPU sleep - and Multi-function Pin Controller (MPC) for flexible I/O assignment. Clock management supports multiple oscillators (HOCO, LOCO, sub-clock, PLL), CAC for accuracy monitoring, and independent domain clocks (ICLK/PCLK/FCLK/ADCLK).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline, 204 CoreMark @ 48 MHz |
| Max Operating Frequency | 48 MHz system clock (ICLK); PCLKB up to 32 MHz, ADCLK up to 48 MHz |
| Memory | 64 KB on-chip flash (no-wait ≤32 MHz), 16 KB SRAM (no wait states), 4 KB data flash (1M erase/write cycles) |
| Analog Peripherals | 12-bit S12ADE A/D converter (15 external + 1 internal channel, 0.67 µs conversion), two 8-bit D/A channels |
| Communication | CAN 2.0B (1 Mbps), six SCI channels (asynchronous/smart card/clock sync), one RIIC (400 kbps), one RSPI (16 Mbps) |
| Package & Temp | PLQP0064KB-C: 64-pin LFQFP, 10 × 10 mm, 0.5 mm pitch; operating range –40 to +85°C |
| Power & Low Power | 1.8–5.5 V single supply; software standby current 0.25 µA (typ.), wake-up time 6.2 µs (HOCO 32 MHz) |
Pinout & Package
Package: PLQP0064KB-C - 64-pin Low-profile Quad Flat Package, 10 × 10 mm body, 0.5 mm pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual power domains: VCC powers digital/analog circuits; VSS is common reference with dedicated decoupling path via VCL |
| XTAL / EXTAL | Main clock oscillator interface | Supports crystal (1–20 MHz) or external clock input; enables precise timing for real-time control loops |
| MTIOC0A–MTIOC4D | MTU2 waveform I/O | 16-bit multi-function timer pins supporting PWM, complementary output, phase counting, and A/D trigger generation |
| RXD1/TXD1, RXD5/TXD5, etc. | SCI serial data I/O | Up to six independent SCI channels with configurable baud rate, LSB/MSB order, and ELC event linking |
| SCL0 / SDA0 | I²C bus interface | Open-drain I²C master/slave interface compliant with SMBus, supporting fast mode (400 kbps) |
| CTX0–CTX31 | Capacitive touch sensing inputs | CTSU2SL supports self-capacitance up to 32 keys on this 64-pin variant; enables robust touch HMI without external IC |
| RES# | Active-low reset input | Asynchronous hardware reset; combined with LVD and IWDT for fail-safe system recovery |
Key Features
| Feature | Design Value |
|---|---|
| Event Link Controller (ELC) | Enables 48 event sources to directly trigger peripheral operations (e.g., MTU start, A/D conversion) without CPU intervention or interrupt latency |
| Background Operation (BGO) | Allows simultaneous execution of user code and data flash reprogramming, critical for field firmware updates without system halt |
| IEC60730 Safety Support | Integrated self-test functions for A/D converter, clock accuracy (CAC), IWDT, RAM (via DOC), and analog input disconnection detection |
| Capacitive Touch Sensing Unit | CTSU2SL provides 32-key self-capacitance support on this package; eliminates need for external touch controller in cost-sensitive HMI designs |
| Low-Power Timer (LPT) | 16-bit timer operating in software standby mode using sub-clock or IWDT oscillator, enabling ultra-low-power periodic wake-up (e.g., sensor polling every 100 ms) |
Applications
| Industrial Motor Control | Smart Home HMI Panel |
|---|---|
Use Scenario: Closed-loop speed/position control of BLDC motors in HVAC blowers or pump drives using sensorless FOC algorithms. IC Role / Device Role / Timing Role: Primary controller executing motor control firmware, generating complementary PWM via MTU2, sampling current/voltage via 12-bit A/D, and managing CAN diagnostics. Use Value: Integrated 48 MHz RXv2 core with FPU accelerates trigonometric calculations; 0.67 µs A/D conversion enables high-bandwidth current sampling; CAN interface supports J1939/EtherCAT slave gateway functions. | Use Scenario: Touch-enabled wall-mounted thermostat with local display, environmental sensing, and Wi-Fi/BLE connectivity via UART bridge. IC Role / Device Role / Timing Role: Local HMI processor handling capacitive touch decoding, temperature/humidity ADC reads, RTC-based scheduling, and UART-to-bridge communication. Use Value: On-chip CTSU2SL supports 32-key touch panel without external IC; 16 KB SRAM accommodates GUI frame buffer; software standby mode draws only 0.25 µA between touch events. |
| Factory Asset Monitor | Medical Sensor Node |
Use Scenario: Battery-powered vibration/temperature monitor mounted on rotating machinery, transmitting alerts via CAN or RSPI to gateway. IC Role / Device Role / Timing Role: Edge data acquisition node performing analog sensor conditioning, FFT preprocessing (using DSP instructions), and low-duty-cycle wireless transmission. Use Value: 204 CoreMark performance enables real-time spectral analysis; dual 8-bit D/A outputs drive analog test signals; 4 KB data flash stores calibration coefficients with 1M endurance. | Use Scenario: Portable pulse oximeter requiring precise analog front-end, low-noise signal processing, and battery life >72 hours. IC Role / Device Role / Timing Role: Signal acquisition and processing unit digitizing photodiode outputs via 12-bit A/D, applying digital filtering, and driving OLED via SPI. Use Value: 12-bit A/D with per-channel sampling time control minimizes noise aliasing; temperature sensor and internal reference enable drift compensation; 1.8 V operation extends coin-cell battery life. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F51405ADFM#30 | 128 KB flash, 32 KB SRAM, 8 KB data flash; same package, same peripherals except RTC and CTSU2L | Required for larger firmware images or extended data logging; lacks RTC but retains CTSU2SL (32-key touch) | Select when firmware size exceeds 64 KB or long-term timestamped logging is needed without RTC dependency |
| R5F51403ADFJ#30 | 32-pin LQFP (7 × 7 mm, 0.8 mm pitch), reduced I/O count (23 GPIO), no CAN, no CTSU, fewer SCI channels | Targeted at space-constrained, cost-optimized nodes where touch and CAN are unnecessary | Choose for minimal-footprint sensor endpoints where 64-pin features are over-specified and BOM cost is critical |
Compared with R5F51403ADFM#30, R5F51405ADFM#30 offers double flash/SRAM for complex control stacks but omits RTC, while R5F51403ADFJ#30 sacrifices CAN, touch, and I/O count for footprint reduction - making the R5F51403ADFM#30 the optimal balance of integration, size, and industrial feature set.
Availability
R5F51403ADFM#30 is available at Aetrix Electronics and suitable for industrial motor control, smart home HMI panels, factory asset monitors, and medical sensor nodes requiring stable component supply across production lifecycles.
Supply support for R5F51403ADFM#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX140 Group targets cost-sensitive, low-power industrial and consumer applications requiring rich analog integration, touch capability, functional safety support, and seamless connectivity - all within compact packages like the R5F51403ADFM#30.
FAQ
What is the maximum operating frequency and core type of the R5F51403ADFM#30?
The R5F51403ADFM#30 features a 32-bit RXv2 CPU core with a maximum operating frequency of 48 MHz. It achieves 204 CoreMark at this speed and includes an IEEE-754-compliant 32-bit floating-point unit, on-chip 32×32-bit multiplier, and 2-cycle divider - enabling efficient real-time control and signal processing tasks without external coprocessors.
Does the R5F51403ADFM#30 include a real-time clock (RTC) module?
No, the R5F51403ADFM#30 does not include a real-time clock (RTCB) module. According to Table 1.2 in the datasheet, RTC is supported only in 80-pin and certain 48-pin variants of the RX140 Group, but explicitly omitted in the 64-pin PLQP0064KB-C package used by the R5F51403ADFM#30. Applications requiring timekeeping must implement external RTC or use low-power timer with sub-clock source.
How many capacitive touch keys does the R5F51403ADFM#30 support?
The R5F51403ADFM#30 supports up to 32 capacitive touch keys using the CTSU2SL unit in self-capacitance mode. This is confirmed in Table 1.2, which specifies "32 channels" for CTSU2SL in the 64-pin LFQFP (PLQP0064KB-C) configuration - matching the R5F51403ADFM#30's package and memory variant.
What communication interfaces are available on the R5F51403ADFM#30?
The R5F51403ADFM#30 includes one CAN 2.0B module (1 Mbps), six SCI channels (with asynchronous, clock-sync, and smart card modes), one I²C bus interface (400 kbps, SMBus-compatible), and one RSPI channel (16 Mbps). It does not include the RSCAN module's full mailbox count or CTSU2L mutual-capacitance mode due to its 64-pin package constraints.
Is the R5F51403ADFM#30 suitable for IEC60730-compliant appliance control?
Yes, the R5F51403ADFM#30 includes dedicated hardware features for IEC60730 Class B compliance, including self-diagnostic support for the A/D converter, clock frequency accuracy measurement circuit (CAC), independent watchdog timer (IWDT), RAM test assistance via DOC, and analog input disconnection detection - all documented in the "Useful functions for IEC60730 compliance" section of the datasheet.
R5F51403ADFM#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX140
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 48MHz
- Connectivity:
- I2C, SCI, SPI
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 53
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 16K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 5.5V
- Data Converters:
- A/D 15x12b; D/A 2x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F51403ADFM#30 FAQ
1.How can I place an order for R5F51403ADFM#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F51403ADFM#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F51403ADFM#30 reliable?
The price and inventory of R5F51403ADFM#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F51403ADFM#30 is usually 5 days.
3.What payment methods are accepted for R5F51403ADFM#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F51403ADFM#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F51403ADFM#30?
R5F51403ADFM#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F51403ADFM#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F51403ADFM#30?
For technical support, including R5F51403ADFM#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F51403ADFM#30 requirements.
6.How does Aetrix verify that R5F51403ADFM#30 is sourced from the original manufacturer or authorized distributors?
All R5F51403ADFM#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F51403ADFM#30 meets industry standards.
7.What is the process for return or replacement of R5F51403ADFM#30?
All R5F51403ADFM#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F51403ADFM#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F51403ADFM#30 part is unused and in its original packaging.
Return procedure for R5F51403ADFM#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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