Renesas R5F51406BDNE#30
- Part No.:
- R5F51406BDNE#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
R5F51406BDNE#30.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 48WFQFN
- Quantity:
- Payment:

- Shipping:

Inventory:832
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F51406BDNE#30 from Renesas is a 32-bit RXv2 core MCU operating at up to 48 MHz, featuring 256 KB flash, 64 KB SRAM, 8 KB data flash, on-chip FPU, AES-128/256 hardware accelerator, and capacitive touch sensing (CTSU2SL) supporting up to 24 keys in self-capacitance mode - deployed in industrial HMI and smart sensor nodes requiring secure, low-power timing and analog interface.
For engineers reviewing the R5F51406BDNE#30 datasheet, R5F51406BDNE#30 pinout, R5F51406BDNE#30 application, or R5F51406BDNE#30 equivalent, this page delivers verified package mapping (PWQN0048KC-A, 48-pin HWQFN, 7 × 7 mm, 0.5 mm pitch), confirmed peripheral set (1-channel CAN, 3× SCIg, 1× RIIC, 1× RSPI, 12-bit S12ADE with 11 external channels), real-time clock omission, and encryption module inclusion - all validated against Renesas R01DS0379EJ0120 Rev.1.20.
Technical Context
The R5F51406BDNE#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions, delivering 204 CoreMark at 48 MHz. It integrates an IEEE-754-compliant 32-bit FPU, 32-bit multiplier, and 32-bit divider with two-cycle latency.
Its low-power architecture supports four modes including software standby (0.25 µA typ.) with 6.2 µs wake-up from HOCO 32 MHz, and includes ELC for event-driven peripheral coordination without CPU intervention - enabling deterministic response in battery-powered control loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 204 CoreMark @ 48 MHz |
| Max Operating Frequency | 48 MHz system clock (ICLK), with PCLKB up to 32 MHz and FCLK up to 48 MHz |
| Memory | 256 KB on-chip flash (no-wait ≤32 MHz), 64 KB SRAM (no-wait), 8 KB data flash (1M erase cycles) |
| Analog Peripherals | 12-bit S12ADE A/D converter with 11 external + 1 internal channels, 0.67 µs conversion time @ 48 MHz ADCLK |
| Communication | 1× CAN (ISO11898-1, 1 Mbps), 3× SCIg (asynchronous/clock-sync/smart card), 1× RIIC (400 kbps), 1× RSPI (16 Mbps) |
| Security & Sensing | AESA hardware accelerator (AES-128/256, ECB/CBC/CTR), RNGA true random generator, CTSU2SL capacitive touch (24-key self-cap) |
| Operating Range | 1.8 V to 5.5 V supply, –40°C to +85°C ambient (D-grade), PWQN0048KC-A package (7 × 7 mm, 0.5 mm pitch) |
Pinout & Package
PWQN0048KC-A is a 48-pin HWQFN package (7 × 7 mm body, 0.5 mm pitch) with exposed thermal pad, rated for –40°C to +85°C operation. Pin functions are multiplexed via MPC and support 5-V-tolerant inputs on selected pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual power domains: VCC powers digital/analog circuits; VCL–VSS capacitor stabilizes internal LDO |
| XTAL / EXTAL | Main clock oscillator interface | Supports crystal (1–20 MHz) or external clock input; enables precise timing for RTC and communication baud rates |
| MTIOC0A–MTIOC4D | MTU2 waveform I/O | 6-channel 16-bit timer outputs supporting complementary PWM, phase counting, and A/D trigger generation |
| RXD1/TXD1, RXD5/TXD5, RXD6/TXD6 | SCIg serial I/O | Three independent asynchronous UART interfaces with fine-adjustable baud rate (0–255/255) and ELC event linking |
| SCL0 / SDA0 | RIIC bus interface | Open-drain I²C master/slave port compliant with SMBus, supporting fast-mode (400 kbps) for sensor hub connectivity |
| TXD12 / RXD12 | SCIh LIN-compatible interface | Dedicated LIN bus channel with start-frame detection and information-frame protocol support for automotive subsystems |
| CTX0–CTX23 | CTSU2SL touch electrode inputs | 24 dedicated pins for self-capacitance touch keys; no external components required for basic HMI implementation |
| RES# | Active-low reset input | Asynchronous hardware reset with internal pull-up; initiates full system initialization and register clearing |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware execution enables real-time motor control math without software emulation overhead |
| Event Link Controller (ELC) | Direct hardware routing of 48 event signals eliminates interrupt latency and CPU polling in closed-loop sensor-to-PWM systems |
| Capacitive Touch Unit (CTSU2SL) | Self-capacitance mode supports 24 keys with automatic correction/judgment - reduces BOM cost vs. external touch controllers |
| Hardware AES Accelerator | AESA block performs 128-bit AES encryption in 176 cycles, enabling secure firmware updates and encrypted sensor data transmission |
| Low-power standby mode | 0.25 µA typical current draw with LPT active allows multi-year battery life in wireless sensor endpoints |
Applications
| Industrial HMI Panel | Smart Thermostat Node |
|---|---|
Use Scenario: Wall-mounted HVAC interface with touch buttons, temperature display, and local fan control logic. IC Role / Device Role / Timing Role: Main controller executing UI rendering, sensor fusion (temp/humidity), and PWM fan drive using MTU2 and S12ADE. Use Value: Integrated CTSU2SL eliminates external touch IC; AES ensures secure OTA updates; 48-MHz RXv2 handles real-time UI responsiveness. | Use Scenario: Battery-powered room thermostat with BLE gateway interface, ambient sensing, and valve actuation. IC Role / Device Role / Timing Role: System-on-chip managing ADC sampling, low-power sleep/wake scheduling, and secure sensor data packaging. Use Value: 0.25 µA software standby extends CR2032 battery life beyond 5 years; RNGA + AES enable TLS handshake offload. |
| Programmable Logic Controller (PLC) I/O Module | Motor Drive Feedback Interface |
Use Scenario: DIN-rail mounted digital I/O expansion module with isolated inputs, relay outputs, and Modbus RTU over RS485. IC Role / Device Role / Timing Role: Protocol engine and GPIO manager interfacing with RSPI-connected isolators and SCIg-linked RS485 transceivers. Use Value: Three SCIg channels support dual Modbus ports; ELC synchronizes input capture with output PWM edges for deterministic I/O timing. | Use Scenario: Brushless DC motor control board collecting hall-effect encoder signals, current sense ADC, and generating gate-drive PWM. IC Role / Device Role / Timing Role: Real-time motion controller using MTU2 phase-counting mode, S12ADE double-trigger ADC, and complementary PWM outputs. Use Value: 16-bit MTU2 with 6 channels provides full 3-phase commutation timing; 0.67 µs ADC enables high-bandwidth current loop closure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F51406ADNE#30 | No AES or RNG hardware; identical package, memory, and peripheral set otherwise | Suitable for cost-sensitive designs where cryptographic operations are handled in software or external co-processor | Select when security acceleration is unnecessary and BOM cost reduction is prioritized over firmware update security |
| R5F51405BDNE#30 | 128 KB flash / 32 KB RAM / 8 KB data flash; same encryption, CTSU2SL, and peripheral count except no CAN module | Targeted at simpler sensor nodes or UI-only devices without fieldbus connectivity requirements | Choose when CAN is unused and reduced memory footprint lowers code size and power consumption |
Compared with R5F51406ADNE#30 and R5F51405BDNE#30, the R5F51406BDNE#30 uniquely combines full 256 KB flash, hardware AES/RNG, and CAN while retaining the compact 48-pin HWQFN footprint - making it optimal for secure, connected edge controllers where space and cryptographic integrity are both constraints.
Availability
R5F51406BDNE#30 is available at Aetrix Electronics and suitable for industrial HMI panels, smart thermostat nodes, PLC I/O modules, and motor drive feedback interfaces requiring stable component supply across extended product lifecycles.
Supply support for R5F51406BDNE#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets.
The RX140 Group targets cost-optimized, low-power 32-bit applications demanding integrated security, capacitive touch, and real-time analog processing - designed specifically for smart sensors, HMI, and industrial control edge nodes.
FAQ
What is the maximum operating frequency and core type of the R5F51406BDNE#30?
The R5F51406BDNE#30 features a 32-bit RXv2 CPU core with a maximum operating frequency of 48 MHz. It achieves 204 CoreMark at that speed and includes a 5-stage pipeline, variable-length instruction set, and IEEE-754-compliant floating-point unit. The R5F51406BDNE#30 uses on-chip high-speed oscillators (HOCO) or external crystals up to 20 MHz with PLL multiplication to reach 48 MHz, ensuring deterministic real-time performance for industrial control tasks.
Does the R5F51406BDNE#30 include hardware encryption capabilities?
Yes, the R5F51406BDNE#30 includes the AESA hardware accelerator supporting AES-128 and AES-256 in ECB, CBC, and CTR modes, plus the RNGA true random number generator. These modules are enabled by the "B" suffix in the part number and are absent in "A" variants like R5F51406ADNE#30. The R5F51406BDNE#30 executes 128-bit AES encryption in 176 cycles, enabling efficient secure boot and OTA firmware updates without CPU overhead.
What is the package type and pin count of the R5F51406BDNE#30?
The R5F51406BDNE#30 uses the PWQN0048KC-A package: a 48-pin HWQFN with 7 × 7 mm body size and 0.5 mm pitch, including an exposed thermal pad. This package is specified for –40°C to +85°C operation (D-grade) and supports 5-V-tolerant inputs on designated pins. The "NE" in the part number explicitly denotes this HWQFN variant per Renesas' naming convention in R01DS0379EJ0120.
How many A/D converter channels does the R5F51406BDNE#30 support, and what is its conversion speed?
The R5F51406BDNE#30 integrates the S12ADE 12-bit A/D converter with 11 external input channels and 1 internal channel (temperature sensor). Its minimum conversion time is 0.67 µs per channel when ADCLK runs at 48 MHz. The R5F51406BDNE#30 supports scan modes, sampling time per channel configuration, conversion result comparison, and double-trigger mode for motor control - all confirmed in Table 1.2 of the datasheet for the 48-pin HWQFN variant.
Does the R5F51406BDNE#30 support CAN communication, and if so, which standard?
Yes, the R5F51406BDNE#30 includes one RSCAN CAN module compliant with ISO11898-1, supporting both standard and extended frames at up to 1 Mbps. This capability is retained in the 48-pin HWQFN package per Table 1.2, distinguishing it from lower-pin-count variants like R5F51403ADNE#30. The R5F51406BDNE#30 uses 16 mailboxes and supports message filtering and loopback testing - essential for industrial fieldbus integration.
R5F51406BDNE#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-WFQFN Exposed Pad
- Series:
- RX140
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 48MHz
- Connectivity:
- CANbus, I2C, SCI, SPI
- Peripherals:
- AES, Capacitive Touch, DMA, LVD, POR, PWM, Temp Sensor, TRNG, WDT
- Number of I/O:
- 39
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 5.5V
- Data Converters:
- A/D 11x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F51406BDNE#30 FAQ
1.How can I place an order for R5F51406BDNE#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F51406BDNE#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F51406BDNE#30 reliable?
The price and inventory of R5F51406BDNE#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F51406BDNE#30 is usually 5 days.
3.What payment methods are accepted for R5F51406BDNE#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F51406BDNE#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F51406BDNE#30?
R5F51406BDNE#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F51406BDNE#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F51406BDNE#30?
For technical support, including R5F51406BDNE#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F51406BDNE#30 requirements.
6.How does Aetrix verify that R5F51406BDNE#30 is sourced from the original manufacturer or authorized distributors?
All R5F51406BDNE#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F51406BDNE#30 meets industry standards.
7.What is the process for return or replacement of R5F51406BDNE#30?
All R5F51406BDNE#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F51406BDNE#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F51406BDNE#30 part is unused and in its original packaging.
Return procedure for R5F51406BDNE#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F51406BDNE#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

