Renesas R5F523E6LGFP#50
- Part No.:
- R5F523E6LGFP#50
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
R5F523E6LGFP#50.pdf
- Description:
- 32BIT MCU RX23E-B, DSAD 125KSPS,
- Quantity:
- Payment:

- Shipping:

Inventory:4,804
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F523E6LGFP#50 from Renesas is a 32-bit RXv2 microcontroller optimized for high-precision analog measurement in industrial sensing applications. It integrates a 24-bit delta-sigma ADC with ±10-V input capability, rail-to-rail programmable gain instrumentation amplifier (gain = 1–128), 256 KB on-chip flash, 32 KB SRAM, and CAN 2.0B interface - all operating at up to 32 MHz. Target use includes load cell signal conditioning, weigh scale controllers, and precision process transmitters.
For engineers reviewing the R5F523E6LGFP#50 datasheet, R5F523E6LGFP#50 pinout, R5F523E6LGFP#50 application, or R5F523E6LGFP#50 equivalent, key selection criteria include its 125 kSPS delta-sigma sampling rate, ±10-V HVAIN support, integrated excitation current sources (50–1000 µA), low-drift voltage reference (2.5 V, 8 ppm/°C), and IEC60730-compliant self-test features for functional safety-critical designs.
Technical Context
The R5F523E6LGFP#50 implements the RXv2 CPU core with IEEE 754-compliant 32-bit FPU and DSP extensions, enabling real-time floating-point sensor compensation algorithms. Its analog subsystem centers on the DSADB unit synchronized to PCLKC (≤16 MHz), with configurable sinc filters, simultaneous 50/60 Hz rejection, and hardware-assisted disconnect detection for ±10-V differential inputs.
Power management includes three low-power modes (sleep, deep sleep, software standby), LPT operation during standby, and voltage monitoring across three independent LVD circuits. Clocking supports main (1–20 MHz), sub (32.768 kHz), and on-chip oscillators, with CAC for frequency accuracy validation - critical for time-sensitive metrology and calibration routines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 32 MHz max, 64 DMIPS, IEEE 754 FPU, MPU, 256 interrupt vectors |
| Flash / RAM / Data Flash | 256 KB code flash (no-wait @32 MHz), 32 KB SRAM (no-wait), 8 KB data flash (1M erase cycles) |
| 24-bit Delta-Sigma ADC | 8-channel differential input, ±10-V HVAIN pins, 125 kSPS max, 24-bit effective resolution @3.8 SPS |
| PGA & Analog Front End | Rail-to-rail PGA (×1–×128), 11 nVRMS noise @gain=128, offset drift 4 nV/°C, two 50–1000 µA excitation sources |
| Voltage Reference | 2.5 V internal VREF (8 ppm/°C drift, ±10 mA), ±10-V input range supported, external reference selectable |
| Communication Interfaces | CAN 2.0B (1 Mbps), 6× SCIg, 1× SCIh (LIN), 1× RIIC (400 kbps), 1× RSPI (16 Mbps), 1× RSCAN |
| Package & Temp Range | PLQP0100KB-B: 100-pin LFQFP, 14 × 14 mm, 0.5 mm pitch; operating temperature –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0100KB-B - 100-pin Low-Profile Quad Flat Package, 14 mm × 14 mm body, 0.5 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Core power supply / ground | 1.8–5.5 V single-supply operation; separate AVCC0 (4.5–5.5 V) required for 12-bit ADC and ±10-V analog front end |
| HVAIN0–HVAIN3 | High-voltage analog inputs | ±10-V differential input pins supporting load cells and strain gauges; internally routed to DSADB with PGA bypass option |
| IEXC0 / IEXC1 | Excitation current outputs | Programmable 50–1000 µA current sources with ±0.2% matching; used for RTD/bridge sensor biasing |
| DSAD_VREFH / DSAD_VREFL | Delta-sigma ADC reference | Accepts external reference or internal 2.5 V; enables ratiometric measurement stability against supply variation |
| CAN_TX / CAN_RX | CAN bus physical layer interface | Dedicated differential pair compliant with ISO 11898-1; supports 1 Mbps operation with built-in protocol controller |
| MTU0–MTU5 | Multi-function timer pulse outputs | 6× 16-bit channels supporting complementary PWM, phase counting, and A/D trigger generation for synchronized acquisition |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Hardware-assisted RAM test (DOC), A/D self-diagnostic, clock accuracy monitoring (CAC), IWDT fault detection |
| Simultaneous 50/60 Hz Rejection | Configurable sinc filter combinations enable real-time line-frequency noise cancellation at 10/54 SPS output rates |
| Low-Drift Analog Subsystem | PGA gain drift ≤1 ppm/°C (gain=1–16), offset drift ≤4 nV/°C (gain=64–128), 2.5 V VREF with 8 ppm/°C tempco |
| Event Link Controller (ELC) | Enables autonomous peripheral triggering (e.g., MTU → DSADB start) without CPU wake-up - reduces latency and power in sleep modes |
| High-Voltage Input Protection | HVAIN pins tolerate ±10 V with integrated disconnect detection and fault reporting via VDET module |
| Background Operation (BGO) | Data flash programming/erasing proceeds concurrently with CPU execution - no interruption to real-time control loops |
Applications
| Industrial Weigh Scale Controller | High-Accuracy Process Transmitter |
|---|---|
|
Use Scenario: Digital weighing system for tank-level or conveyor-belt mass measurement using 4-wire load cells. IC Role / Device Role / Timing Role: Primary signal conditioner and controller: digitizes mV-level bridge outputs via ±10-V HVAIN, applies digital filtering and temperature compensation, and communicates weight data over CAN. Use Value: 24-bit effective resolution at 3.8 SPS eliminates external signal-chain components; integrated excitation sources and PGA reduce BOM count by ≥3 ICs. |
Use Scenario: 4–20 mA/HART transmitter for pressure/temperature sensors in hazardous area field devices. IC Role / Device Role / Timing Role: Metrology engine and communication hub: acquires sensor data with <5 µV offset drift, performs linearization, and drives RSPI-connected HART modem. Use Value: IEC60730 self-test functions satisfy SIL2 diagnostic coverage requirements; 105°C rating enables operation in hot enclosures without derating. |
| Strain Gauge-Based Structural Monitor | Multi-Sensor Smart Sensor Node |
|
Use Scenario: Battery-powered structural health monitor measuring micro-strain on bridges or wind turbine blades. IC Role / Device Role / Timing Role: Ultra-low-power analog front end and edge processor: samples strain gauge outputs at 125 kSPS, runs FFT-based anomaly detection, and wakes only on threshold events. Use Value: Software standby mode with LPT enables years of operation on coin-cell; ±10-V input handles full-scale bridge excitation without external attenuators. |
Use Scenario: Industrial IoT node aggregating RTD, thermocouple, and voltage inputs for predictive maintenance analytics. IC Role / Device Role / Timing Role: Multi-sensor fusion controller: sequences excitation currents across 2× IEXC channels, synchronizes DSADB and S12AD conversions, and timestamps data via RTC. Use Value: Single-chip integration of 24-bit DSADB, 12-bit S12AD, dual excitation sources, and CAN eliminates inter-IC timing skew and PCB routing complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-precision analog microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F523E6NGFP#50 | Same package and core, but 5-V analog input range (not ±10 V); 31.25 kSPS max DSADB sampling | Suitable for lower-range sensors (e.g., 0–5 V industrial voltage outputs) where ±10-V HVAIN capability is unnecessary | Select when cost sensitivity outweighs need for high-voltage sensor interfacing and maximum DSADB throughput |
| R5F523E5LGFP#50 | Same 10-V analog range and LCD support, but reduced memory: 128 KB flash / 16 KB RAM / 8 KB data flash | Targeted at space-constrained designs with simpler firmware and no requirement for large OTA update partitions or complex UI buffers | Choose when application firmware fits within 128 KB and real-time processing demands do not require 32 KB SRAM buffer space |
Compared with R5F523E6NGFP#50 and R5F523E5LGFP#50, the R5F523E6LGFP#50 uniquely delivers full ±10-V HVAIN support combined with 125 kSPS DSADB throughput and 256 KB flash - making it the only variant qualified for high-dynamic-range, high-speed industrial metrology where both input range and sampling bandwidth are simultaneously critical.
Availability
R5F523E6LGFP#50 is available at Aetrix Electronics and suitable for industrial weigh scale controllers, high-accuracy process transmitters, and structural health monitors requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for R5F523E6LGFP#50 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RX23E-B Group - including the R5F523E6LGFP#50 - was designed specifically for high-precision analog measurement in industrial automation, targeting applications demanding integrated metrology-grade signal chains with functional safety support.
FAQ
What is the maximum sampling rate of the 24-bit delta-sigma ADC in the R5F523E6LGFP#50?
The R5F523E6LGFP#50 supports a maximum delta-sigma ADC sampling rate of 125 kSPS. This is achievable with modulator clock fMOD = 4 MHz and appropriate sinc filter configuration. At lower data rates (e.g., 3.8 SPS), the device achieves 24-bit effective resolution with simultaneous 50/60 Hz rejection - a capability confirmed in the DSADB section of the R01DS0402EJ0100 datasheet.
Does the R5F523E6LGFP#50 support ±10-V analog inputs, and which pins are used?
Yes, the R5F523E6LGFP#50 supports ±10-V differential analog inputs via dedicated HVAIN0–HVAIN3 pins (pins 73–76, 83–86 per Table 1.4). These pins connect directly to the DSADB unit and are validated for ±10-V operation in the "Analog front end (AFEA)" section of the datasheet, including integrated voltage fault detection and disconnect assist.
What is the operating temperature range specified for the R5F523E6LGFP#50?
The R5F523E6LGFP#50 is a G-version device rated for operation from –40°C to +105°C ambient temperature. This is explicitly defined in Table 1.3 (List of Products) and Figure 1.1 (Part Number Decoding), where the "G" suffix denotes the extended industrial temperature grade - critical for deployment in hot enclosures or outdoor industrial environments.
How many excitation current sources does the R5F523E6LGFP#50 integrate, and what are their specifications?
The R5F523E6LGFP#50 integrates two fully programmable excitation current sources (IEXC0 and IEXC1), each configurable from 50 µA to 1000 µA in six discrete steps. Per the datasheet, they provide ±0.2% current matching and 5 ppm/°C drift matching - enabling precise, matched biasing of 3- or 4-wire RTDs and resistive bridge sensors without external DACs or op-amps.
Is the R5F523E6LGFP#50 pin-compatible with other members of the RX23E-B Group in the same package?
Yes, all RX23E-B Group devices in the PLQP0100KB-B (100-pin LFQFP) package - including R5F523E6LGFP#50, R5F523E6NGFP#50, and R5F523E5LGFP#50 - share identical pinouts and mechanical footprint. Functional differences (e.g., HVAIN support, DSADB speed, memory size) are implemented internally; no PCB redesign is needed when migrating between these variants.
R5F523E6LGFP#50 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- -
- Core Size:
- -
- Speed:
- -
- Connectivity:
- -
- Peripherals:
- -
- Number of I/O:
- -
- Program Memory Size:
- -
- Program Memory Type:
- -
- EEPROM Size:
- -
- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- -
- Oscillator Type:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
R5F523E6LGFP#50 FAQ
1.How can I place an order for R5F523E6LGFP#50 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F523E6LGFP#50 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F523E6LGFP#50 reliable?
The price and inventory of R5F523E6LGFP#50 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F523E6LGFP#50 is usually 5 days.
3.What payment methods are accepted for R5F523E6LGFP#50?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F523E6LGFP#50 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F523E6LGFP#50?
R5F523E6LGFP#50 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F523E6LGFP#50 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F523E6LGFP#50?
For technical support, including R5F523E6LGFP#50 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F523E6LGFP#50 requirements.
6.How does Aetrix verify that R5F523E6LGFP#50 is sourced from the original manufacturer or authorized distributors?
All R5F523E6LGFP#50 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F523E6LGFP#50 meets industry standards.
7.What is the process for return or replacement of R5F523E6LGFP#50?
All R5F523E6LGFP#50 units undergo pre-shipment inspection (PSI). If there is an issue with R5F523E6LGFP#50, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F523E6LGFP#50 part is unused and in its original packaging.
Return procedure for R5F523E6LGFP#50:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F523E6LGFP#50 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

