Renesas R5F523E6MGFL#10
- Part No.:
- R5F523E6MGFL#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
R5F523E6MGFL#10.pdf
- Description:
- 32BIT MCU RX23E-B 256K LFQFP48 F
- Quantity:
- Payment:

- Shipping:

Inventory:3,057
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F523E6MGFL#10 from Renesas is a 32-bit RXv2 core MCU optimized for high-precision analog measurement in industrial sensor nodes and metering systems. It integrates a 24-bit delta-sigma ADC with 31.25 kSPS max sampling rate, ±5-V input range, rail-to-rail programmable gain instrumentation amplifier (gain = 1–128), on-chip excitation current sources (50–1000 µA), and 256 KB flash/32 KB SRAM - all operating at up to 32 MHz within a 48-pin LFQFP package.
For engineers reviewing the R5F523E6MGFL#10 datasheet, R5F523E6MGFL#10 pinout, R5F523E6MGFL#10 application, or R5F523E6MGFL#10 equivalent, this device supports IEC60730-compliant self-diagnostic A/D calibration, CAN 2.0B communication at 1 Mbps, and low-power software standby with active LPT - critical for smart grid sensors, load cell interfaces, and precision weight scales requiring stable 24-bit measurement under varying supply and temperature conditions.
Technical Context
The R5F523E6MGFL#10 implements the RXv2 CPU core with IEEE 754-compliant 32-bit FPU, 64 DMIPS @ 32 MHz, and memory protection unit (MPU) for functional safety. Its analog subsystem centers on the DSADB module synchronized to PCLKC (≤16 MHz), featuring fourth- and fifth-order sinc digital filters, simultaneous 50/60 Hz rejection at 10/54 SPS, and offset/gain error calibration.
It supports event-driven operation via ELC to trigger ADC conversions, PWM outputs, or D/A updates without CPU intervention - enabling deterministic timing in closed-loop control. The MCU operates across 1.8–5.5 V with three low-power modes, including software standby where only the low-power timer (LPT) and IWDT remain active using the 32.768 kHz sub-clock or dedicated 15-kHz oscillator.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline, 64 DMIPS @ 32 MHz |
| Max Operating Frequency | 32 MHz - enables real-time signal processing of 24-bit ADC data at 31.25 kSPS |
| Flash / SRAM / Data Flash | 256 KB / 32 KB / 8 KB - supports field firmware updates and nonvolatile calibration storage |
| 24-bit Delta-Sigma ADC | 31.25 kSPS max sampling rate, ±5-V input range, 11 nVRMS noise @ gain=128, 4 nV/°C offset drift |
| PGA Gain Range | ×1 to ×128 - configurable per channel to match transducer output levels without external amplification |
| Excitation Current Sources | Two channels, 50–1000 µA with ±0.2% matching - drives resistive bridge sensors with minimal thermal error |
| Communication Interfaces | CAN 2.0B (1 channel, 1 Mbps), SCI (3 channels), I²C (1 channel, 400 kbps), RSPI (1 channel, 16 Mbps) |
| Operating Temperature | –40°C to +85°C - qualified for industrial ambient environments without derating |
Pinout & Package
Package: PLQP0048KB-B - 48-pin LFQFP, 7 mm × 7 mm, 0.5 mm pitch, exposed pad for thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Core and I/O supply pins; requires local decoupling per Renesas layout guidelines |
| AVCC0 / AVSS0 | Analog power / Analog ground | Isolated analog domain for DSADB and S12ADE; must be separated from digital planes |
| HVAIN0–HVAIN3 | High-voltage analog inputs | ±5-V differential input pins supporting direct connection to strain gauges and RTDs |
| IEXC0 / IEXC1 | Excitation current outputs | Programmable current sources for 4-wire bridge biasing; matched to ±0.2% |
| DSADREFP / DSADREFN | Delta-sigma ADC reference inputs | Differential reference pair accepting external 2.5 V or internal VREF (2.5 V ±8 ppm/°C) |
| MTIOA0–MTIOA5 | MTU2a waveform outputs | Complementary PWM outputs for motor control or power stage gate driving |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | UART interface for debug, configuration, or host communication; supports bit-rate modulation |
| CAN_TX / CAN_RX | CAN physical layer interface | Dedicated differential pair compliant with ISO 11898-1; requires external transceiver |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Self-Diagnostic Support | Integrated A/D converter disconnect detection, clock accuracy measurement (CAC), RAM test assistance via DOC, and IWDT diagnostics - reduces certification effort for Class B safety applications |
| Simultaneous 50/60 Hz Rejection | Configurable sinc filter modes enable precise line-frequency noise cancellation at 10/54 SPS - essential for AC-coupled sensor measurements in noisy industrial settings |
| Event Link Controller (ELC) | Hardware-triggered ADC conversion, PWM update, or D/A output without CPU wake-up - lowers system power and improves timing determinism |
| Rail-to-Rail Programmable Gain Amplifier | Input common-mode range extends to AVSS0 and AVCC0; eliminates need for level-shifting circuitry when interfacing with bipolar sensors |
| Low-Power Software Standby Mode | LPT continues counting using sub-clock or IWDT oscillator while CPU and most peripherals are halted - enables microamp-level sleep current with wake-on-event capability |
| On-Chip Voltage Reference | 2.5 V ±8 ppm/°C drift over –40 to +85°C - provides stable reference for DSADB and S12ADE without external components |
Applications
| Industrial Load Cell Interface | Smart Electricity Meter Sensor Node |
|---|---|
Use Scenario: High-accuracy weight measurement in platform scales and hopper load cells using full-bridge strain gauges. IC Role / Device Role / Timing Role: Primary signal acquisition MCU handling excitation, PGA gain selection, 24-bit delta-sigma conversion, and CAN-based reporting. Use Value: 31.25 kSPS sampling with 24-bit resolution and ±0.2% excitation matching ensures <0.01% full-scale error across temperature - meeting OIML R76 Class III requirements. |
Use Scenario: Isolated sensor front-end in polyphase electricity meters measuring voltage, current, and power quality parameters. IC Role / Device Role / Timing Role: Analog acquisition engine synchronizing DSADB sampling to zero-crossing detection via ELC-triggered interrupts. Use Value: Simultaneous 50/60 Hz rejection at 54 SPS enables accurate RMS calculation without external notch filters - reducing BOM cost and PCB area. |
| Temperature-Compensated Pressure Transmitter | Factory Automation Analog Input Module |
Use Scenario: 4–20 mA loop-powered pressure transmitter with integrated temperature compensation and HART modulation. IC Role / Device Role / Timing Role: Dual-role controller managing DSADB-based pressure sensing, TEMPS-based cold-junction compensation, and 16-bit D/A for loop current generation. Use Value: On-chip 2.5 V reference (8 ppm/°C) and ±5-V HVAIN inputs allow direct ratiometric measurement of bridge outputs - eliminating external reference drift errors. |
Use Scenario: Modular I/O card for PLC backplanes acquiring signals from thermocouples, RTDs, and 4–20 mA transmitters. IC Role / Device Role / Timing Role: Multi-channel analog hub performing simultaneous sampling, linearization, and CANopen message formatting. Use Value: 8-channel 12-bit S12ADE (1.4 µs conversion) handles fast-response signals like valve position feedback, while DSADB manages high-resolution sensor inputs - consolidating two ADC functions into one chip. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-precision analog measurement MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F523E5MGFL#10 | 128 KB flash / 16 KB SRAM; identical analog peripheral set and package | Lower code footprint requirement; suitable for simpler firmware with no OTA update or complex math libraries | Select when application fits within 128 KB flash and does not require floating-point intensive algorithms or large calibration tables |
| ADUCM360BCPZ-RL7 | ARM Cortex-M3 core; 24-bit ΣΔ ADC with 3.75 kSPS max; integrated 4 mA–20 mA DAC driver | Optimized for 4–20 mA loop-powered devices; lacks CAN, RTC, and ELC; lower max sampling rate | Prefer for loop-powered transmitters where analog integration outweighs need for high-speed communication or event chaining |
Compared with R5F523E5MGFL#10, the R5F523E6MGFL#10 offers double flash/SRAM for advanced firmware features and floating-point math, while ADUCM360BCPZ-RL7 trades MCU performance and interface flexibility for tighter analog integration in loop-powered designs - making R5F523E6MGFL#10 optimal for CAN-connected, multi-sensor industrial nodes requiring both speed and precision.
Availability
R5F523E6MGFL#10 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart metering systems, and factory automation I/O modules requiring stable component supply, long-term lifecycle support, and guaranteed -40°C to +85°C operation.
Supply support for R5F523E6MGFL#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and IoT applications - with over 40 years of MCU innovation and functional safety expertise.
The RX23E-B Group targets high-precision measurement systems requiring integrated 24-bit delta-sigma ADCs, programmable gain amplifiers, and IEC60730 compliance - designed specifically for industrial sensors, energy meters, and process control instrumentation.
FAQ
What is the maximum sampling rate supported by the 24-bit delta-sigma ADC in R5F523E6MGFL#10?
The R5F523E6MGFL#10 supports a maximum sampling rate of 31.25 kSPS for its 24-bit delta-sigma ADC (DSADB). This rate is achieved with modulator clock fMOD = 4 MHz and appropriate sinc filter configuration. At lower rates (e.g., 10 or 54 SPS), the device enables simultaneous 50/60 Hz rejection - a key capability for noise-immune industrial sensing. The R5F523E6MGFL#10 datasheet specifies this value in Table 1.1 and Section 1.1.
Does R5F523E6MGFL#10 include an integrated voltage reference, and what is its accuracy?
Yes, the R5F523E6MGFL#10 includes an on-chip 2.5 V voltage reference (VREF) with ±8 ppm/°C temperature drift over –40°C to +85°C. It delivers ±10 mA output current and serves as the default reference for both the 24-bit DSADB and 12-bit S12ADE converters. This eliminates the need for external references in most precision applications - a feature confirmed in Section 1.1 and Table 1.1 of the R5F523E6MGFL#10 datasheet.
Can R5F523E6MGFL#10 operate in low-power modes while maintaining analog measurement capability?
Yes, the R5F523E6MGFL#10 supports software standby mode where the CPU and most peripherals halt, yet the low-power timer (LPT) and independent watchdog timer (IWDT) remain active. The DSADB can be triggered via ELC events during standby, enabling periodic wake-up and measurement without full CPU activation - critical for battery-operated sensor nodes. This behavior is documented in Section 1.1 and Figure 1.2 of the R5F523E6MGFL#10 datasheet.
What package type and pin count does R5F523E6MGFL#10 use?
The R5F523E6MGFL#10 uses the PLQP0048KB-B package: a 48-pin low-profile quad flat package (LFQFP), 7 mm × 7 mm body size, 0.5 mm pin pitch, with an exposed thermal pad. This matches the "FL" suffix in the part number per Figure 1.1 of the R5F523E6MGFL#10 datasheet. It provides 17 general-purpose I/O pins, 4 high-voltage analog inputs (HVAIN), and dedicated analog power/ground pins for noise-sensitive measurement.
How does R5F523E6MGFL#10 support IEC60730 functional safety compliance?
The R5F523E6MGFL#10 integrates hardware-assisted self-test features required for Class B IEC60730 compliance, including A/D converter disconnect detection, clock frequency accuracy measurement (CAC), RAM test assistance via the data operation circuit (DOC), and independent watchdog timer (IWDT) diagnostics. These capabilities reduce software validation burden and are explicitly listed in the "Useful functions for IEC60730 compliance" section of the R5F523E6MGFL#10 datasheet.
R5F523E6MGFL#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-LQFP
- Series:
- RX23E-B
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 32MHz
- Connectivity:
- CANbus, I2C, SCI, SPI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 17
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 5.5V
- Data Converters:
- A/D 8x12b SAR, 6x24b Sigma-Delta; D/A 1x16b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F523E6MGFL#10 FAQ
1.How can I place an order for R5F523E6MGFL#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F523E6MGFL#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F523E6MGFL#10 reliable?
The price and inventory of R5F523E6MGFL#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F523E6MGFL#10 is usually 5 days.
3.What payment methods are accepted for R5F523E6MGFL#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F523E6MGFL#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F523E6MGFL#10?
R5F523E6MGFL#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F523E6MGFL#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F523E6MGFL#10?
For technical support, including R5F523E6MGFL#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F523E6MGFL#10 requirements.
6.How does Aetrix verify that R5F523E6MGFL#10 is sourced from the original manufacturer or authorized distributors?
All R5F523E6MGFL#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F523E6MGFL#10 meets industry standards.
7.What is the process for return or replacement of R5F523E6MGFL#10?
All R5F523E6MGFL#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F523E6MGFL#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F523E6MGFL#10 part is unused and in its original packaging.
Return procedure for R5F523E6MGFL#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F523E6MGFL#10 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

