Renesas R5F562GAADFP#V3
- Part No.:
- R5F562GAADFP#V3
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F562GAADFP#V3.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,359
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F562GAADFP#V3 from Renesas Electronics is a 100-MHz 32-bit RX CPU-based microcontroller in the RX62G Group, designed for industrial motor control and power conversion systems. It integrates dual 12-bit ADC units (4 channels each) with sample-and-hold, programmable gain amplifiers, and window comparators; a 10-bit ADC (12 channels); 8× MTU3 timers supporting two three-phase complementary PWM outputs; CAN interface; and 16 KB SRAM with 256 KB flash. It operates across –40°C to +85°C and supports IEC 60730 safety compliance.
For engineers reviewing the R5F562GAADFP#V3 datasheet, R5F562GAADFP#V3 pinout, R5F562GAADFP#V3 application, or R5F562GAADFP#V3 equivalent, key selection criteria include its 100-MHz PWM timing resolution (312 ps delay control), simultaneous 7-channel ADC sampling capability, integrated POE3 for hardware fault shutdown, CAN bus support, and G version temperature rating compatibility.
Technical Context
The R5F562GAADFP#V3 implements the RXv1 CPU core with IEEE-754 single-precision FPU, 165 DMIPS performance at 100 MHz, and memory protection unit (MPU). Its clock system includes PLL-based ICLK up to 100 MHz and PCLK up to 50 MHz, with independent division/multiplication paths for CPU and peripherals.
It features three A/D converter units: two 12-bit S12ADA units (each with 3-channel sample-and-hold, PGA, and window comparator) and one 10-bit ADA unit (12 channels), all capable of synchronized trigger initiation via MTU3/GPT. The MTU3 unit delivers non-overlapping complementary PWM with automatic dead-time generation and phase-counting mode for inverter control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS |
| Flash Memory | 256 KB main flash, zero wait states at full CPU speed |
| SRAM | 16 KB on-chip SRAM, no wait states for instruction/operand access |
| ADC System | Dual 12-bit S12ADA (4 ch × 2 units) + single 10-bit ADA (12 ch); simultaneous 7-channel sampling supported |
| PWM Capability | MTU3: 8× 16-bit channels; supports two independent three-phase complementary PWM outputs with hardware dead-time insertion |
| Communication | CAN 2.0B (32 mailboxes), 3× SCI, 1× RIIC, 1× RSPI, 1× LIN master |
| Operating Temp | –40°C to +85°C (D version), qualified per IEC 60730 Class B |
| Supply Voltage | 5-V operation: VCC/PLLVCC = 4.0–5.5 V; AVCC/AVCC0 = 4.0–5.5 V |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 mm × 14 mm, 0.5 mm pitch, RoHS-compliant, lead-free (Sn only).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core logic supply (VCC) and reference ground (VSS) pins; decoupling required per datasheet layout guidelines |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | Primary complementary PWM output pins for motor gate drive; support hardware dead-time and fault shutdown via POE3 |
| AD000–AD007, AD100–AD103, AD200–AD211 | Analog input channels | Input terminals for 12-bit S12ADA (units 0/1) and 10-bit ADA; mapped to internal PGA, S/H, and comparator circuits |
| CAN_TX, CAN_RX | CAN physical layer interface | Differential transceiver pins compliant with ISO 11898-1; require external termination and common-mode choke |
| SCI0_TXD, SCI0_RXD | Asynchronous serial interface | Full-duplex UART pins with built-in noise cancellation; support baud rates up to 15 Mbps at 100 MHz ICLK |
| POE0, POE4, POE8, POE10, POE11 | Port Output Enable inputs | Hardware fault detection inputs triggering immediate high-impedance state on MTU3/GPT output pins for safe shutdown |
Key Features
| Feature | Design Value |
|---|---|
| IEC 60730 Class B Support | Integrated self-test functions: ADC self-diagnosis, CRC calculator, oscillation stop detection, and PORT register monitoring |
| Hardware PWM Timing Precision | GPTa unit enables 312 ps PWM edge delay resolution (at 100 MHz ICLK), critical for precise inverter dead-time tuning |
| Simultaneous Multi-Channel Sampling | Three ADC units can initiate synchronized conversions across 7 channels-enabling real-time current/voltage vector acquisition |
| Programmable Gain Amplifier | 11-step gain (2.0× to 13.333×) per 12-bit ADC channel, eliminating need for external signal conditioning in motor current sensing |
| Complementary PWM Fault Protection | POE3 hardware block directly disables MTU3/GPT outputs within <1 µs upon overcurrent or comparator trip-no CPU intervention required |
| Memory Protection Unit (MPU) | Configurable region-based access control for flash, SRAM, and peripheral registers-essential for ASIL-B software partitioning |
Applications
| Industrial Motor Drives | Uninterruptible Power Supplies (UPS) |
|---|---|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Primary controller executing FOC algorithm, generating synchronized PWM waveforms, sampling phase currents via dual 12-bit ADCs, and managing CAN-based supervisory communication. Use Value: Hardware-accelerated MTU3 PWM with automatic dead-time and POE3 fault response ensures safe inverter switching under transient overload conditions. | Use Scenario: Real-time AC/DC and DC/AC conversion control in online double-conversion UPS systems with battery backup. IC Role / Device Role / Timing Role: Master controller coordinating rectifier, inverter, and battery charge stages; performing voltage/current regulation, harmonic compensation, and grid synchronization. Use Value: Simultaneous 7-channel ADC sampling captures line voltage, DC bus, and output current waveforms in one cycle-enabling fast digital PLL and adaptive filtering. |
| Solar Inverters | Industrial PLC I/O Modules |
Use Scenario: MPPT tracking and grid-tie inverter control in string and central solar inverters operating up to 1000 V DC input. IC Role / Device Role / Timing Role: High-precision analog front-end controller interfacing with isolated current sensors, executing fast MPPT algorithms, and generating isolated gate-drive signals. Use Value: Integrated 12-bit ADC with programmable gain amplifier directly interfaces shunt-based current sensors without external op-amps-reducing BOM cost and board area. | Use Scenario: Analog input/output expansion module in modular PLC systems requiring high-accuracy sensor signal conditioning and actuator drive. IC Role / Device Role / Timing Role: Local intelligence node handling 16-channel analog input acquisition, 4-channel analog output generation, and CANopen device communication. Use Value: On-chip data flash (32 KB, 30,000 write cycles) stores calibration coefficients and configuration parameters-enabling field-updatable sensor linearization without external EEPROM. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F562TAADFP#V3 | Same RX62T Group package and pinout; includes CAN interface (R5F562GAADFP#V3 lacks CAN) | Required where CAN-based distributed motor control or J1939 diagnostics are mandatory | Select R5F562TAADFP#V3 when CAN bus integration is needed; otherwise R5F562GAADFP#V3 offers identical PWM/ADC performance at lower cost |
| R5F562G7ADFP#V3 | Same RX62G Group, but reduced memory: 128 KB flash / 8 KB SRAM / 8 KB data flash vs. 256/16/32 KB | Suitable for cost-sensitive, functionally trimmed motor control designs with smaller firmware footprint | Choose R5F562G7ADFP#V3 for simplified applications where full 256 KB flash and dual 12-bit ADC buffers are unnecessary |
Compared with R5F562TAADFP#V3, the R5F562GAADFP#V3 omits CAN but retains identical PWM timing precision, ADC architecture, and POE3 fault protection-making it optimal for standalone inverter modules. Against R5F562G7ADFP#V3, it provides double flash/SRAM capacity and enhanced ADC resources for complex real-time control loops.
Availability
R5F562GAADFP#V3 is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, solar inverters, and PLC I/O modules requiring stable component supply, long-term lifecycle assurance, and IEC 60730-certified silicon.
Supply support for R5F562GAADFP#V3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX62G Group-including R5F562GAADFP#V3-is engineered specifically for high-performance, safety-critical industrial motor control and power conversion, emphasizing deterministic PWM timing, robust analog sensing, and functional safety compliance.
FAQ
What is the maximum operating frequency and CPU performance of the R5F562GAADFP#V3?
The R5F562GAADFP#V3 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using the 32-bit RXv1 CPU core. It includes a single-precision IEEE-754 floating-point unit and a 64-bit accumulator for high-precision motor control calculations. This performance level is confirmed in Renesas' R01DS0096EJ0200 datasheet, page 1.
Does the R5F562GAADFP#V3 support CAN communication?
No, the R5F562GAADFP#V3 does not include the CAN module. Per Table 1.3 in the R01DS0096EJ0200 datasheet, the "A" suffix in the part number denotes CAN support, while "D" (as in R5F562GAADFP#V3) indicates CAN is not implemented. For CAN-enabled variants, consider R5F562TAADFP#V3 or R5F562GAAGFP#V3.
What ADC resources are integrated into the R5F562GAADFP#V3?
The R5F562GAADFP#V3 integrates three A/D converter units: two independent 12-bit S12ADA units (4 channels each, with sample-and-hold, programmable gain amplifiers, and window comparators) and one 10-bit ADA unit (12 channels). All units support simultaneous 7-channel sampling triggered by MTU3 or GPT timers, as specified in Section 1.1 and Table 1.1 of R01DS0096EJ0200.
What package type and pin count does the R5F562GAADFP#V3 use?
The R5F562GAADFP#V3 uses the PLQP0100KB-A package: a 100-pin LQFP measuring 14 mm × 14 mm with 0.5 mm pitch, RoHS-compliant and lead-free (Sn finish). This matches the "FP" suffix in the part number and is documented in Table 1.3 and Page 6 of R01DS0096EJ0200.
Is the R5F562GAADFP#V3 qualified for functional safety standards?
Yes, the R5F562GAADFP#V3 includes hardware features required for IEC 60730 Class B compliance, including self-diagnostic ADC, CRC calculator, oscillation stop detection, independent watchdog timer (IWDT), and PORT register monitoring. These capabilities are explicitly cited in the "Features" section (page 1) and Table 1.1 of R01DS0096EJ0200.
R5F562GAADFP#V3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 55
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 16K x 8
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 5.5V
- Data Converters:
- A/D 12x10b, 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F562GAADFP#V3 FAQ
1.How can I place an order for R5F562GAADFP#V3 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F562GAADFP#V3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F562GAADFP#V3 reliable?
The price and inventory of R5F562GAADFP#V3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F562GAADFP#V3 is usually 5 days.
3.What payment methods are accepted for R5F562GAADFP#V3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F562GAADFP#V3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F562GAADFP#V3?
R5F562GAADFP#V3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F562GAADFP#V3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F562GAADFP#V3?
For technical support, including R5F562GAADFP#V3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F562GAADFP#V3 requirements.
6.How does Aetrix verify that R5F562GAADFP#V3 is sourced from the original manufacturer or authorized distributors?
All R5F562GAADFP#V3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F562GAADFP#V3 meets industry standards.
7.What is the process for return or replacement of R5F562GAADFP#V3?
All R5F562GAADFP#V3 units undergo pre-shipment inspection (PSI). If there is an issue with R5F562GAADFP#V3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F562GAADFP#V3 part is unused and in its original packaging.
Return procedure for R5F562GAADFP#V3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F562GAADFP#V3 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

