Renesas R5F562T6DDFM#V3
- Part No.:
- R5F562T6DDFM#V3
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F562T6DDFM#V3.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 64LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F562T6DDFM#V3 from Renesas Electronics is a 64-pin, 5-V supply, CAN-disabled variant of the RX62T Group 32-bit MCU, operating at up to 100 MHz with 64 Kbytes flash, 8 Kbytes SRAM, and 8 Kbytes data flash. It integrates dual 12-bit ADC units (4 channels each), one 10-bit ADC (12 channels), MTU3 timers for three-phase PWM control, GPT for complementary single-phase PWM, and supports IEC 60730-compliant motor control in industrial inverters.
For engineers reviewing the R5F562T6DDFM#V3 datasheet, R5F562T6DDFM#V3 pinout, R5F562T6DDFM#V3 application, or R5F562T6DDFM#V3 equivalent, key selection criteria include its 64-pin LQFP-0.5mm package, absence of CAN interface, D-version temperature range (–40°C to +85°C), and dedicated motor-control peripherals including POE3-triggered fault protection and simultaneous 7-channel ADC sampling.
Technical Context
The R5F562T6DDFM#V3 implements the 32-bit RX CPU core with IEEE-754 single-precision FPU, 165 DMIPS performance at 100 MHz, and memory-protection unit (MPU) for safety-critical firmware. Its clock system supports PLL-based ICLK up to 100 MHz and PCLK up to 50 MHz, with independent division/multiplication for system and peripheral domains.
It features eight 16-bit MTU3 channels supporting two three-phase complementary PWM outputs with automatic dead-time insertion, plus four 16-bit GPT channels enabling four single-phase or one three-phase + one single-phase complementary PWM outputs - all with CPU-load-free waveform generation and comparator-linked control for real-time motor feedback loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard architecture with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz ICLK; enables 100-MHz PWM timing resolution and sub-microsecond ADC conversion |
| Memory | 64 Kbytes main flash (no wait states), 8 Kbytes SRAM, 8 Kbytes reprogrammable data flash (30k cycles) |
| Analog Peripherals | Dual 12-bit S12ADA (4 ch × 2 units, 3 sample-and-hold circuits, programmable gain amplifier), one 10-bit ADA (12 ch), simultaneous 7-channel sampling capability |
| PWM & Timers | 8× MTU3 (16-bit, 3-phase complementary PWM), 4× GPT (16-bit, single/three-phase complementary PWM), POE3 fault-triggered high-impedance output control |
| Operating Voltage & Temp | 5-V supply (VCC/PLLVCC = 4.0–5.5 V; AVCC = 4.0–5.5 V); industrial temp range –40°C to +85°C (D version) |
| Package | LQFP64 (PLQP0064KB-A), 10×10 mm, 0.5 mm pitch, 61 I/O + 21 input-only pins |
Pinout & Package
Package: PLQP0064KB-A - 64-pin LQFP, 10×10 mm body, 0.5 mm pitch, lead-free (Sn only), tray packaging (#V).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Dedicated 5-V digital supply pins; multiple VSS pins ensure low-noise grounding for analog and digital domains |
| AVCC, AVSS | Analog power and ground | Separate 5-V analog supply domain isolates noise-sensitive ADC and comparator circuitry |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | 12 large-current PWM output pins supporting three-phase inverter drive with non-overlapping outputs |
| GPTIO0A–GPTIO3B | GPT waveform I/O | 8 complementary PWM pins configurable for single-phase or three-phase motor control with dead-time generation |
| AN000–AN111 | Analog inputs | 20 total ADC input channels (12× 10-bit + 8× 12-bit), with shared and per-unit sample-and-hold circuits |
| POE0, POE4, POE8, POE10, POE11 | Port Output Enable triggers | Five fault-detection inputs that force MTU3/GPT pins into high-impedance state on overcurrent or comparator trip |
Key Features
| Feature | Design Value |
|---|---|
| IEC 60730 Compliance Support | Integrated self-diagnostic ADC, CRC calculator, oscillation stop detection, and IWDT with LOCO clock ensure Class B functional safety certification readiness |
| CPU-Off PWM Generation | MTU3 and GPT generate complementary PWM waveforms without CPU intervention, freeing processor for sensor fusion or communication tasks |
| Simultaneous Multi-Channel Sampling | Three ADC units coordinate to sample 7 channels concurrently - critical for vector-controlled PMSM/BLDC current and voltage monitoring |
| Programmable Gain Amplifier (PGA) | 11-step gain (2.0× to 13.333×) per 12-bit ADC unit enables direct shunt-resistor current sensing across wide dynamic range |
| Hardware Fault Protection | POE3 logic responds to comparator trips or short-circuit detection within <1 µs to disable PWM outputs - meets SIL-2 response time requirements |
Applications
| Industrial Motor Drives | Home Appliance Inverters |
|---|---|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase PMSM motors in HVAC compressors and washing machine drum drives. IC Role / Device Role / Timing Role: Primary motor controller executing real-time FOC algorithm, generating synchronized PWM, sampling phase currents via simultaneous 7-channel ADC, and enforcing hardware fault shutdown. Use Value: Enables precise torque ripple suppression and >95% efficiency through 100-MHz PWM timing, 12-bit ADC resolution, and sub-µs fault response. | Use Scenario: Sensorless BLDC motor control in refrigerator fans and vacuum cleaner suction systems. IC Role / Device Role / Timing Role: Executes back-EMF zero-crossing detection, generates variable-frequency PWM, monitors DC-link voltage/current, and manages LIN communication with system MCU. Use Value: Reduces BOM cost by integrating LIN master, 10-bit ADC for voltage sensing, and GPT-based commutation timing - no external timer or transceiver required. |
| Industrial PLC I/O Modules | Power Tool Battery Management |
Use Scenario: Analog input expansion module acquiring thermocouple, RTD, and 4–20 mA loop signals in modular PLC racks. IC Role / Device Role / Timing Role: High-accuracy signal conditioner with PGA, window comparators, and CRC-protected data transfer to host controller via RSPI. Use Value: Achieves ±0.1% measurement accuracy using dual 12-bit ADCs with internal reference calibration and self-diagnostic voltage generation. | Use Scenario: Smart battery pack controller managing cell balancing, temperature monitoring, and charge/discharge FET control in cordless power tools. IC Role / Device Role / Timing Role: Safety-monitoring MCU performing periodic cell voltage checks, thermal shutdown via IWDT, and CAN-free communication with host tool MCU via SCI. Use Value: Eliminates need for external watchdog or precision voltage references - IWDT with dedicated LOCO and 12-bit ADC with internal VREFH0 generation enable full BMS autonomy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F562T6ADFM#V3 | Same package and memory, but includes CAN 2.0B interface (32 mailboxes) | Required where CAN bus integration is needed for multi-axis coordination or diagnostics | Select when system-level communication mandates CAN; otherwise R5F562T6DDFM#V3 reduces cost and EMI complexity |
| R5F562T7DDFM#V3 | Same package and temperature grade, but 128 Kbytes flash, 8 Kbytes SRAM, 8 Kbytes data flash | Suitable for larger firmware images with integrated communication stacks or OTA update capability | Choose when application code size exceeds 64 Kbytes or requires background data flash updates without halting execution |
Compared with R5F562T6ADFM#V3, R5F562T6DDFM#V3 removes CAN hardware to reduce pin count contention and EMI susceptibility in space-constrained inverter designs; versus R5F562T7DDFM#V3, it trades flash capacity for lower cost and power in fixed-function motor controllers where firmware footprint is stable and minimal.
Availability
R5F562T6DDFM#V3 is available at Aetrix Electronics and suitable for industrial motor drives, home appliance inverters, PLC analog I/O modules, and power tool battery management systems requiring stable component supply, long-term lifecycle support, and IEC 60730-compliant design assurance.
Supply support for R5F562T6DDFM#V3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX62T Group, including R5F562T6DDFM#V3, was designed specifically for high-performance, safety-certifiable motor control applications - integrating real-time PWM, precision analog, and functional safety accelerators in a single chip.
FAQ
What is the maximum operating frequency and CPU performance of the R5F562T6DDFM#V3?
The R5F562T6DDFM#V3 operates at a maximum system clock (ICLK) frequency of 100 MHz and delivers 165 DMIPS of processing performance. Its 32-bit RX CPU core includes a single-precision IEEE-754 floating-point unit, barrel shifter, and 64-bit accumulator - enabling efficient execution of motor control algorithms such as field-oriented control and sensorless commutation without external math coprocessors.
Does the R5F562T6DDFM#V3 support CAN communication?
No, the R5F562T6DDFM#V3 does not support CAN. The "D" in its part number suffix indicates CAN functionality is disabled. This variant is optimized for applications where CAN is unnecessary - such as standalone inverter modules or cost-sensitive appliances - reducing electromagnetic emissions and simplifying PCB layout compared to CAN-enabled variants like R5F562T6ADFM#V3.
What ADC resources are available on the R5F562T6DDFM#V3?
The R5F562T6DDFM#V3 integrates three A/D converter units: two 12-bit S12ADA units (4 channels each, with sample-and-hold, programmable gain amplifiers, and window comparators) and one 10-bit ADA unit (12 channels). All three units support simultaneous 7-channel sampling, enabling synchronized acquisition of motor phase currents and DC-link voltage for real-time control loop execution.
What package type and pin count does the R5F562T6DDFM#V3 use?
The R5F562T6DDFM#V3 uses the PLQP0064KB-A package: a 64-pin LQFP with 10×10 mm body size and 0.5 mm pitch. It provides 61 general-purpose I/O pins and 21 input-only pins, including dedicated large-current outputs for MTU3 and GPT PWM signals, and five POE3 trigger inputs for hardware fault response.
How does the R5F562T6DDFM#V3 support IEC 60730 functional safety compliance?
The R5F562T6DDFM#V3 supports IEC 60730 Class B compliance through integrated hardware features: independent watchdog timer (IWDT) with dedicated 125-kHz LOCO clock, oscillation stop detection, self-diagnostic ADC with internal reference generation, CRC calculator for memory and data integrity checking, and PORT register monitoring. These features enable systematic verification of MCU health without software overhead.
R5F562T6DDFM#V3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 37
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 5.5V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F562T6DDFM#V3 FAQ
1.How can I place an order for R5F562T6DDFM#V3 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F562T6DDFM#V3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F562T6DDFM#V3 reliable?
The price and inventory of R5F562T6DDFM#V3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F562T6DDFM#V3 is usually 5 days.
3.What payment methods are accepted for R5F562T6DDFM#V3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F562T6DDFM#V3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F562T6DDFM#V3?
R5F562T6DDFM#V3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F562T6DDFM#V3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F562T6DDFM#V3?
For technical support, including R5F562T6DDFM#V3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F562T6DDFM#V3 requirements.
6.How does Aetrix verify that R5F562T6DDFM#V3 is sourced from the original manufacturer or authorized distributors?
All R5F562T6DDFM#V3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F562T6DDFM#V3 meets industry standards.
7.What is the process for return or replacement of R5F562T6DDFM#V3?
All R5F562T6DDFM#V3 units undergo pre-shipment inspection (PSI). If there is an issue with R5F562T6DDFM#V3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F562T6DDFM#V3 part is unused and in its original packaging.
Return procedure for R5F562T6DDFM#V3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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