Renesas R5F562T7ADFM#V1
- Part No.:
- R5F562T7ADFM#V1
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F562T7ADFM#V1.pdf
- Description:
- IC MCU 32BIT 128KB FLASH 64LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,098
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F562T7ADFM#V1 from Renesas is a 100-MHz 32-bit RX CPU-based microcontroller in the RX62T Group, designed for high-precision motor control and industrial inverter applications. It integrates dual 12-bit ADC units (4 channels each) with sample-and-hold, programmable gain amplifiers, and window comparators; four 16-bit GPT channels supporting complementary PWM with dead-time generation; and CAN interface compliant with ISO 11898-1 - all operating within –40°C to +85°C.
For engineers reviewing the R5F562T7ADFM#V1 datasheet, R5F562T7ADFM#V1 pinout, R5F562T7ADFM#V1 application, or R5F562T7ADFM#V1 equivalent, key selection criteria include its 128-Kbyte flash/8-Kbyte SRAM/8-Kbyte data flash configuration, 64-pin LQFP (PLQP0064KB-A) package with 37 I/O pins, 100-MHz PWM timing resolution, IEC 60730-compliant self-diagnostic A/D and CRC units, and support for three-phase inverter gate drive via MTU3/GPT complementary outputs.
Technical Context
The R5F562T7ADFM#V1 implements the RXv1 CPU core with IEEE-754 single-precision FPU, 165 DMIPS performance at 100 MHz, and memory protection unit (MPU). Its clock system supports PLL-based 100-MHz ICLK and configurable PCLK up to 50 MHz, enabling synchronized operation of CPU, MTU3, GPT, and peripheral modules.
It features three independent A/D converter units: two 12-bit S12ADA units (4 channels each, simultaneous 7-channel sampling capability) and one 10-bit ADA unit (12 channels), all with self-diagnostic functions per IEC 60730. The GPT module delivers 100-MHz PWM with sub-nanosecond delay control (312 ps at 100 MHz), while POE3 enables hardware-triggered high-impedance state control on large-current output pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS, IEEE-754 FPU, 64-bit accumulator |
| Memory | 128 Kbytes flash (no wait states), 8 Kbytes SRAM, 8 Kbytes data flash (30,000 write cycles) |
| Analog Peripherals | Two 12-bit ADC units (4 ch × 2, 1.0 µs conversion @ 50 MHz ADCLK), one 10-bit ADC (12 ch), simultaneous 7-ch sampling |
| PWM & Timers | Four 16-bit GPT channels with complementary PWM, dead-time generation, and 312-ps timing resolution at 100 MHz |
| Communication | CAN 2.0B (ISO 11898-1, 32 mailboxes), 3× SCI, 1× RIIC, 1× RSPI, 1× LIN master (v1.3/2.0/2.1) |
| Package & Environment | 64-pin LQFP (PLQP0064KB-A, 10×10 mm, 0.5-mm pitch), –40°C to +85°C operating range (D version) |
| Safety Compliance | IEC 60730 Class B support: self-diagnostic A/D, CRC calculator, IWDT with LOCO clock, oscillation stop detection |
Pinout & Package
Package: PLQP0064KB-A - 64-pin LQFP, 10×10 mm body, 0.5-mm pitch, lead-free (Sn finish), RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Dual power domains: VCC/PLLVCC = 4.0–5.5 V; AVCC/AVCC0 = 4.0–5.5 V for analog section |
| MTIOC0A–MTIOC3B | MTU3 waveform I/O | 12 dedicated pins for three-phase complementary PWM output (non-overlapping, hardware dead-time) |
| GTIOCA0–GTIOCB3 | GPT waveform I/O | 8 pins supporting four complementary PWM channels (single- or three-phase), with software-configurable dead time |
| AN000–AN003, AN100–AN103, AN200–AN211 | Analog inputs | 12 total A/D input channels: 4× for S12ADA Unit 0, 4× for Unit 1, 12× for 10-bit ADA (shared reference) |
| CANH/CANL | CAN bus differential pair | Direct connection to ISO 11898-1 transceiver; supports 1-Mbps operation with built-in message filtering and 32-mailbox RAM |
Key Features
| Feature | Design Value |
|---|---|
| IEC 60730 Class B Support | Integrated self-test for A/D converters, CRC unit for memory/data integrity, independent watchdog timer (IWDT) with dedicated LOCO clock |
| Motor Control PWM Precision | GPT-based 100-MHz PWM with 312-ps timing resolution and automatic dead-time insertion for inverter gate drive safety |
| Dual 12-bit ADC with Signal Conditioning | Two independent S12ADA units, each with 3-channel sample-and-hold, programmable gain amplifier (11-step), and window comparator |
| Hardware Fault Response | Port Output Enable 3 (POE3) triggers immediate high-impedance state on MTU3/GPT pins upon comparator fault, short-circuit detection, or software command |
| Flexible Clock Architecture | Independent ICLK (8–100 MHz) and PCLK (8–50 MHz) domains; PLL, main oscillator, and 125-kHz LOCO for robust timing redundancy |
Applications
| Industrial Motor Drives | Home Appliance Inverters |
|---|---|
Use Scenario: Closed-loop vector control of 3-phase induction or PMSM motors in HVAC compressors and washing machine drum drives. IC Role / Device Role / Timing Role: Real-time execution of FOC algorithms, synchronized sampling of current/voltage sensors, and generation of non-overlapping gate signals with hardware-enforced dead time. Use Value: Enables <1-µs current loop update rates using dual 12-bit ADCs with simultaneous 7-channel sampling and 100-MHz GPT PWM timing precision. |
Use Scenario: Variable-speed compressor and fan control in refrigerators and air conditioners requiring energy efficiency and acoustic noise reduction. IC Role / Device Role / Timing Role: Sensorless rotor position estimation, sinusoidal PWM generation, and thermal monitoring via integrated A/D with programmable gain amplifiers. Use Value: Reduces external signal conditioning components by integrating 3-channel PGAs and window comparators per ADC unit for overcurrent/overtemperature fault detection. |
| Industrial PLC I/O Modules | Factory Automation Gate Drivers |
Use Scenario: Analog input expansion modules with diagnostics for temperature, pressure, and flow sensing in distributed control systems. IC Role / Device Role / Timing Role: High-accuracy sensor digitization with self-diagnostic A/D, CRC-protected data transfer to host MCU, and CAN-based fieldbus communication. Use Value: Meets IEC 60730 Class B requirements via on-chip CRC calculator, IWDT, and A/D self-test - eliminating need for external safety monitors. |
Use Scenario: Isolated gate driver interface for IGBT/SiC modules in servo drives and CNC motion controllers. IC Role / Device Role / Timing Role: Generation of precisely timed, phase-shifted complementary PWM waveforms with hardware-controlled dead time and fast fault shutdown via POE3. Use Value: Prevents shoot-through in power stages through hardware-enforced dead-time compensation and sub-500-ps PWM edge placement accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F562T7ADFH#V3 | 112-pin LQFP (PLQP0112JA-A), 61 I/O pins, 256-Kbyte flash, same core/peripherals but larger package and memory | Supports more complex motor algorithms and additional analog/digital I/O for multi-axis systems | Select when >37 I/O or >128-Kbyte flash is required; not pin-compatible with R5F562T7ADFM#V1 |
| R5F562T7EDFM#V3 | 3.3-V supply version (VCC/PLLVCC = 2.7–3.6 V), identical 64-pin LQFP package and peripheral set, no CAN | Targeted at low-voltage industrial or battery-backed systems where CAN is unnecessary | Choose for 3.3-V designs without CAN; shares same footprint and most pin functions but differs in power and CAN availability |
Compared with R5F562T7ADFM#V1, R5F562T7ADFH#V3 offers higher I/O count and flash capacity in a larger package, while R5F562T7EDFM#V3 provides identical form factor and peripherals at 3.3 V without CAN - enabling voltage-scaling trade-offs without redesigning PCB layout.
Availability
R5F562T7ADFM#V1 is available at Aetrix Electronics and suitable for industrial motor drives, home appliance inverters, and factory automation gate drivers requiring stable component supply, long-term lifecycle assurance, and IEC 60730-compliant embedded control.
Supply support for R5F562T7ADFM#V1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX62T Group, including R5F562T7ADFM#V1, was engineered specifically for high-performance motor control - integrating precision analog, real-time PWM, and functional safety features into a single chip for inverter and servo applications.
FAQ
What is the maximum operating frequency and CPU performance of the R5F562T7ADFM#V1?
The R5F562T7ADFM#V1 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS performance using the RXv1 32-bit CPU core. It includes a single-precision IEEE-754 floating-point unit and a 64-bit accumulator for high-efficiency motor control math operations - all verified in Renesas' R01DS0096EJ0200 datasheet.
Does the R5F562T7ADFM#V1 support CAN communication, and what standard does it comply with?
Yes, the R5F562T7ADFM#V1 integrates a CAN module compliant with ISO 11898-1 (CAN 2.0B), supporting bit rates up to 1 Mbps and featuring 32 dedicated mailboxes for efficient message filtering and buffering - confirmed in Table 1.2 and Section 1.1 of the official datasheet.
What are the A/D converter specifications of the R5F562T7ADFM#V1, and how many channels support simultaneous sampling?
The R5F562T7ADFM#V1 includes two 12-bit S12ADA units (4 channels each) and one 10-bit ADA unit (12 channels). The two 12-bit units support simultaneous sampling across up to seven channels - a capability explicitly documented in the "Three A/D converter units" section and Table 1.1 of the datasheet.
What package type and pin count does the R5F562T7ADFM#V1 use, and is it RoHS compliant?
The R5F562T7ADFM#V1 uses the PLQP0064KB-A package: a 64-pin LQFP with 10×10 mm body and 0.5-mm pitch. It is lead-free (Sn surface finish) and RoHS compliant, as specified in the "Packages" section (Page 6) and ordering information (Table 1.3) of the R01DS0096EJ0200 datasheet.
How does the R5F562T7ADFM#V1 support IEC 60730 functional safety compliance?
The R5F562T7ADFM#V1 supports IEC 60730 Class B through multiple hardware features: self-diagnostic A/D converters, CRC calculator for memory/data integrity, independent watchdog timer (IWDT) with dedicated 125-kHz LOCO clock, and oscillation stop detection - all detailed in Sections 1.1 and 1.2 of the official Renesas documentation.
R5F562T7ADFM#V1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 37
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 5.5V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F562T7ADFM#V1 FAQ
1.How can I place an order for R5F562T7ADFM#V1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F562T7ADFM#V1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F562T7ADFM#V1 reliable?
The price and inventory of R5F562T7ADFM#V1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F562T7ADFM#V1 is usually 5 days.
3.What payment methods are accepted for R5F562T7ADFM#V1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F562T7ADFM#V1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F562T7ADFM#V1?
R5F562T7ADFM#V1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F562T7ADFM#V1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F562T7ADFM#V1?
For technical support, including R5F562T7ADFM#V1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F562T7ADFM#V1 requirements.
6.How does Aetrix verify that R5F562T7ADFM#V1 is sourced from the original manufacturer or authorized distributors?
All R5F562T7ADFM#V1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F562T7ADFM#V1 meets industry standards.
7.What is the process for return or replacement of R5F562T7ADFM#V1?
All R5F562T7ADFM#V1 units undergo pre-shipment inspection (PSI). If there is an issue with R5F562T7ADFM#V1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F562T7ADFM#V1 part is unused and in its original packaging.
Return procedure for R5F562T7ADFM#V1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F562T7ADFM#V1 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

