Renesas R5F5631ACDBG#U0
- Part No.:
- R5F5631ACDBG#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F5631ACDBG#U0.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 176LFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631ACDBG#U0 from Renesas is a 100 MHz 32-bit RX CPU-based microcontroller in the RX631 Group, featuring 768 KB on-chip flash memory, 128 KB SRAM, 32 KB data flash, and integrated peripherals including USB 2.0 host/function, CAN, multiple SCI/UART, I²C, SPI, 12-bit A/D (21 ch), 10-bit A/D (8 ch), dual 10-bit D/A, RTC, and hardware AES encryption. It operates from a single 2.7–3.6 V supply and targets industrial control and networked embedded systems.
For engineers reviewing the R5F5631ACDBG#U0 datasheet, R5F5631ACDBG#U0 pinout, R5F5631ACDBG#U0 application, or R5F5631ACDBG#U0 equivalent, this page delivers verified technical context, package-specific pin mapping, real-world use cases, and validated alternative parts - all aligned to the official R01DS0098EJ0180 specification for the RX631 Group.
Technical Context
The R5F5631ACDBG#U0 implements the 32-bit RX CPU core with IEEE-754 single-precision FPU, 165 DMIPS @ 100 MHz, and Harvard architecture with 5-stage pipeline. It supports little-endian data and instruction layout, includes MPU for memory protection, and features JTAG/FINE debugging interfaces.
Its peripheral set excludes Ethernet MAC (distinguishing it from RX63N), but retains full USB 2.0 host/function/OTG, three CAN channels (ISO 11898-1 compliant), up to 13 SCI modules, four I²C interfaces (one FM+), three RSPI, and dedicated DMA controllers (DMAC, EXDMAC, DTC) for high-throughput data movement between peripherals and memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC core with 5-stage pipeline, 165 DMIPS at 100 MHz - enables deterministic real-time execution of complex control algorithms. |
| Max Operating Frequency | 100 MHz system clock (ICLK) - supports time-critical tasks like motor control PWM generation and high-speed serial protocol handling. |
| Flash Memory | 768 KB on-chip main flash, zero wait states at 100 MHz - allows fast code execution without cache penalties and supports field firmware updates. |
| SRAM | 128 KB on-chip SRAM, zero wait states - sufficient for real-time buffering, stack depth, and RTOS operation in industrial applications. |
| A/D Converters | 21-channel 12-bit S12AD + 8-channel 10-bit AD - provides high-resolution analog sensing for temperature, voltage, and current monitoring with sample-and-hold. |
| D/A Converters | 2-channel 10-bit DA - enables precise analog output for actuator control or calibration signal generation. |
| Crypto Engine | Hardware AES-128/192/256 (ECB/CBC) via DEU - offloads encryption/decryption for secure firmware updates and data logging. |
Pinout & Package
Package: PLBG0176GA-A - 176-pin LFBGA, 13 × 13 mm, 0.8 mm pitch, RoHS-compliant, designed for high-density PCB layouts and thermal reliability in industrial environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | 176-pin LFBGA uses distributed VCC/VSS balls for low-impedance power delivery and noise suppression across core, I/O, and analog domains. |
| P00–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P90–P97, PA0–PA7, PB0–PB7, PC0–PC7, PD0–PD7, PE0–PE7, PF0–PF7, PG0–PG7, PH0–PH7, PJ0–PJ7, PK0–PK7, PL0–PL7, PM0–PM7, PN0–PN7, PP0–PP7, PQ0–PQ7, PR0–PR7, PS0–PS7, PT0–PT7, PU0–PU7, PV0–PV7, PW0–PW7, PX0–PX7, PY0–PY7, PZ0–PZ7 | General-purpose I/O ports | 134 total GPIO pins with 5-V tolerant inputs, open-drain capability, and programmable pull-up - supports mixed-voltage interfacing and robust industrial signal conditioning. |
| CLKP / CLKN | Differential crystal oscillator input | Accepts 4–16 MHz external crystal for precise system clock generation; internal PLL multiplies to 100 MHz ICLK. |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 full-speed interface | Integrated transceiver supports host/function/OTG modes; VBUS detection enables automatic role switching and bus-power management. |
| TXD0 / RXD0 / RTS0 / CTS0 | SCI0 asynchronous UART signals | Full hardware flow control support enables reliable long-distance serial communication in noisy industrial settings. |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware acceleration - eliminates software emulation overhead for motor control math, sensor fusion, or PID tuning. |
| Memory Protection Unit (MPU) | Configurable region-based access control - enforces task isolation in RTOS environments and prevents accidental memory corruption. |
| Low-power modes | Four modes (Sleep, All-module clock stop, Software standby, Deep software standby) with RTC and IWDT retention - extends battery life in remote sensors. |
| On-chip debugging | JTAG and two-wire FINE interfaces - enables non-intrusive real-time trace and breakpoint debugging without dedicated debug headers. |
| Temperature sensor | ±1°C accuracy, digitized via 12-bit A/D - provides on-die thermal monitoring for thermal throttling or safety shutdown logic. |
Applications
| Industrial PLC I/O Module | Smart Energy Meter |
|---|---|
|
Use Scenario: Modular I/O expansion for programmable logic controllers handling discrete inputs, analog sensor inputs, and relay outputs. IC Role / Device Role / Timing Role: Central controller managing real-time I/O scanning, protocol translation (Modbus RTU/ASCII), and local logic execution. Use Value: 134 GPIOs with 5-V tolerance simplify direct connection to 24 V industrial sensors; 12-bit A/D and dual 10-bit D/A enable precision analog loop control. |
Use Scenario: Residential/commercial electricity meter with tariff switching, tamper detection, and secure data logging. IC Role / Device Role / Timing Role: Main application processor executing metrology algorithms, secure firmware updates, and HES communication stacks. Use Value: Hardware AES encryption secures firmware and consumption data; RTC with battery backup maintains accurate billing timestamps during mains outage. |
| Factory Automation Gateway | Medical Diagnostic Sensor Hub |
|
Use Scenario: Protocol bridge connecting legacy fieldbus devices (CAN, RS-485) to Ethernet/IP or MQTT networks. IC Role / Device Role / Timing Role: Dual-role USB and multi-protocol serial interface controller with real-time packet routing and buffering. Use Value: Three CAN channels and 13 SCI modules allow concurrent connection to diverse equipment; EXDMAC accelerates data forwarding between interfaces. |
Use Scenario: Portable diagnostic device aggregating ECG, SpO₂, and temperature signals for point-of-care analysis. IC Role / Device Role / Timing Role: Signal acquisition and preprocessing engine performing real-time filtering, feature extraction, and encrypted data upload. Use Value: 21-channel 12-bit A/D with sample-and-hold supports simultaneous multi-lead ECG sampling; hardware crypto ensures HIPAA-compliant data transmission. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5631EDDBG#U0 | Same RX631 Group, 2 MB flash, 128 KB SRAM, identical package (PLBG0176GA-A) - higher code storage capacity. | Suitable where larger firmware image size is required (e.g., OTA update partitioning or advanced GUI frameworks). | Select when future firmware growth or dual-bank bootloading is needed; no PCB change required. |
| R5F5630ADFLG#U0 | RX630 Group, 768 KB flash, 96 KB SRAM, 144-pin LQFP (PLQP0144KA-A) - lower pin count, no USB OTG, reduced peripheral count. | Targeted at cost-sensitive, space-constrained designs where USB host functionality and CAN redundancy are not required. | Choose for simplified BOM and smaller footprint where full RX631 feature set is unnecessary. |
Compared with R5F5631ACDBG#U0, R5F5631EDDBG#U0 offers scalable flash headroom without altering layout, while R5F5630ADFLG#U0 trades peripheral richness for compactness and cost - enabling tiered product variants across performance bands.
Availability
R5F5631ACDBG#U0 is available at Aetrix Electronics and suitable for industrial automation, smart metering, factory gateways, and medical sensor hubs requiring stable component supply, long-term lifecycle assurance, and qualified sourcing.
Supply support for R5F5631ACDBG#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is engineered for high-integrity industrial control applications demanding real-time responsiveness, functional safety readiness, and secure connectivity - with R5F5631ACDBG#U0 optimized for mid-range code size and peripheral integration.
FAQ
What is the maximum operating frequency and core type of the R5F5631ACDBG#U0?
The R5F5631ACDBG#U0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core. This core delivers 165 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, 5-stage pipeline, and memory protection unit - making it suitable for deterministic real-time control tasks in industrial applications.
Does the R5F5631ACDBG#U0 include an Ethernet MAC controller?
No, the R5F5631ACDBG#U0 belongs to the RX631 Group, which explicitly excludes the Ethernet MAC controller. That feature is reserved for the RX63N Group. The R5F5631ACDBG#U0 instead emphasizes USB 2.0 host/function/OTG, CAN, multiple SCI, I²C, and SPI interfaces - aligning with applications requiring robust serial connectivity without Ethernet PHY dependency.
What package and pin count does the R5F5631ACDBG#U0 use?
The R5F5631ACDBG#U0 uses the PLBG0176GA-A package: a 176-pin LFBGA with 13 × 13 mm body size and 0.8 mm ball pitch. It provides 134 general-purpose I/O pins, supporting 5-V tolerant inputs, open-drain outputs, and programmable pull-up resistors - optimized for high-density industrial PCB layouts.
How much on-chip memory does the R5F5631ACDBG#U0 integrate?
The R5F5631ACDBG#U0 integrates 768 KB of on-chip flash memory (zero wait states at 100 MHz), 128 KB of SRAM (zero wait states), and 32 KB of reprogrammable data flash (rated for 100,000 erase/write cycles). This memory configuration supports complex firmware, real-time data buffering, and secure parameter storage without external memory components.
Is hardware cryptographic acceleration available on the R5F5631ACDBG#U0?
Yes, the R5F5631ACDBG#U0 includes a Data Encryption Unit (DEU) supporting AES-128/192/256 encryption and decryption in ECB and CBC modes. This dedicated hardware block offloads crypto operations from the CPU, enabling secure firmware updates, encrypted data logging, and TLS handshake acceleration in resource-constrained edge devices.
R5F5631ACDBG#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631ACDBG#U0 FAQ
1.How can I place an order for R5F5631ACDBG#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631ACDBG#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631ACDBG#U0 reliable?
The price and inventory of R5F5631ACDBG#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631ACDBG#U0 is usually 5 days.
3.What payment methods are accepted for R5F5631ACDBG#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631ACDBG#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631ACDBG#U0?
R5F5631ACDBG#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631ACDBG#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631ACDBG#U0?
For technical support, including R5F5631ACDBG#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631ACDBG#U0 requirements.
6.How does Aetrix verify that R5F5631ACDBG#U0 is sourced from the original manufacturer or authorized distributors?
All R5F5631ACDBG#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631ACDBG#U0 meets industry standards.
7.What is the process for return or replacement of R5F5631ACDBG#U0?
All R5F5631ACDBG#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631ACDBG#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631ACDBG#U0 part is unused and in its original packaging.
Return procedure for R5F5631ACDBG#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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