Renesas R5F5631ACDLJ#U0
- Part No.:
- R5F5631ACDLJ#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F5631ACDLJ#U0.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 100TFLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631ACDLJ#U0 from Renesas is a 100 MHz 32-bit RX CPU core microcontroller in the RX631 Group, featuring 768 KB on-chip flash memory, 128 KB SRAM, 32 KB data flash, IEEE-754 single-precision FPU, and integrated 12-bit/10-bit A/D converters - designed for industrial control and networked embedded systems without Ethernet MAC.
For engineers reviewing the R5F5631ACDLJ#U0 datasheet, R5F5631ACDLJ#U0 pinout, R5F5631ACDLJ#U0 application, or R5F5631ACDLJ#U0 equivalent, key selection criteria include its 100 MHz operation, absence of Ethernet controller (distinguishing it from RX63N), 100-pin TFLGA package, -40 to +85°C temperature range, and support for USB 2.0 host/function, CAN, multiple SCI, I²C, and SPI interfaces.
Technical Context
The R5F5631ACDLJ#U0 implements the CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU). It executes at 165 DMIPS and supports little-endian or big-endian data arrangement, with on-chip 32×32→64-bit multiplier and 32/32→32-bit divider.
Its clock system includes main crystal oscillator, subclock, 125-kHz LOCO, 50-MHz HOCO, and PLL frequency synthesizer - enabling independent division/multiplication for ICLK (up to 100 MHz), PCLK (up to 50 MHz), FCLK (up to 50 MHz), and BCLK (up to 50 MHz). The device lacks Ethernet MAC and SDRAM controller, consistent with RX631 Group specification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Flash Memory | 768 KB main flash, no wait states at 100 MHz, on-board programmable |
| SRAM | 128 KB on-chip SRAM, no wait states, supports deep software standby backup |
| Data Flash | 32 KB reprogrammable E² data flash, rated for 100,000 erase/write cycles |
| A/D Converters | 21-channel 12-bit S12AD (1.0 µs conversion @ 50 MHz PCLK) + 8-channel 10-bit AD |
| Communication | USB 2.0 host/function/OTG (full-speed), 3 CAN channels, up to 13 SCI, 4 RIIC, 3 RSPI |
| Package & Temp | PTLG0100JA-A 100-pin TFLGA (7 × 7 mm, 0.65-mm pitch), -40 to +85°C (D version) |
Pinout & Package
Package: PTLG0100JA-A - 100-pin Thin Fine-Pitch Land Grid Array (TFLGA), 7 × 7 mm body, 0.65 mm pitch, 0.75 mm height, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual 2.7–3.6 V core/analog supply; dedicated VREFH reference input; 100-pin layout supports full I/O count and decoupling |
| XTAL / EXTAL | Main clock oscillator interface | Connects to external 4–16 MHz crystal; enables precise timing for real-time control and USB synchronization |
| RESET# | Active-low reset input | Asynchronous hardware reset; compatible with power-on reset (POR) and low-voltage detection (LVD) circuitry |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical layer interface | Full-speed USB transceiver pins; VBUS sensing enables bus-powered mode detection and OTG role negotiation |
| TXDn / RXDn (SCI) | Asynchronous serial communication | Multiple SCI channels support UART-based debugging, sensor interfacing, and protocol bridging (e.g., Modbus RTU) |
| TXDn / RXDn / RTSn / CTSn (SCI) | Hardware flow-controlled SCI | Supports RS-232/RS-485 level-shifter interfaces with full handshaking for industrial fieldbus reliability |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware acceleration enables real-time motor control algorithms and sensor fusion without software emulation overhead |
| Memory Protection Unit (MPU) | Enforces privilege-level access control across flash, SRAM, and peripheral address spaces - critical for IEC 60730 Class B compliance |
| Integrated DEU AES engine | Hardware-accelerated 128/192/256-bit AES encryption/decryption in ECB/CBC modes secures firmware updates and secure boot operations |
| Low-power modes | Four configurable modes (Sleep, All-module clock stop, Software standby, Deep software standby) reduce active current to 500 µA/MHz |
| Temperature sensor | On-die ±1°C accuracy sensor digitized via 12-bit A/D converter - enables thermal monitoring without external components |
Applications
| Industrial PLC I/O Module | Smart Energy Metering |
|---|---|
|
Use Scenario: Compact DIN-rail-mounted I/O expansion module collecting analog sensor inputs and driving relay outputs in factory automation. IC Role / Device Role / Timing Role: Main controller executing deterministic ladder logic, managing SCI/RS-485 fieldbus, and performing real-time A/D sampling at 1 kHz per channel. Use Value: 768 KB flash stores complex control firmware; 128 KB SRAM buffers multi-axis motion profiles; 12-bit A/D ensures <1 LSB linearity for 4–20 mA loop calibration. |
Use Scenario: DIN-rail energy meter with tariff switching, harmonic analysis, and secure DLMS/COSEM over PLC or RF mesh. IC Role / Device Role / Timing Role: System-on-chip handling metrology calculations, secure firmware updates, and dual-port communication (M-Bus + RF SoC interface). Use Value: Hardware AES-256 encrypts metering data; USB OTG enables field technician configuration; 100 MHz CPU sustains 50/60 Hz fundamental + 50th harmonic FFT in real time. |
| Building Automation Controller | Medical Diagnostic Peripheral |
|
Use Scenario: BACnet MS/TP or KNX IP gateway aggregating HVAC sensor data and actuating valve drivers across distributed zones. IC Role / Device Role / Timing Role: Protocol translation hub with concurrent SCI (BACnet), I²C (temperature/humidity sensors), and CAN (valve position feedback). Use Value: 13 SCI channels enable simultaneous legacy fieldbus support; 32 KB data flash logs event history with wear leveling; RTC with battery backup maintains schedule integrity during AC loss. |
Use Scenario: Portable ultrasound probe interface module acquiring analog front-end signals and transmitting processed image frames to host tablet via USB. IC Role / Device Role / Timing Role: Real-time signal processor interfacing with ADCs, generating PWM for piezoelectric transducer excitation, and streaming compressed frames over USB 2.0. Use Value: FPU accelerates beamforming math; 100 MHz clock ensures sub-microsecond timer resolution for echo time-of-flight measurement; 128 KB SRAM buffers raw RF data before compression. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5631BDDLJ#U0 | 1 MB flash, same 128 KB SRAM, identical package and peripherals | Higher firmware capacity for feature-rich HMI or protocol stacks requiring >768 KB code space | Select when bootloader, OTA update partition, and application logic exceed 768 KB footprint |
| R5F5630ADFL#U0 | 64-pin LQFP, 768 KB flash, 64 KB SRAM, no USB OTG, reduced SCI count (5 channels) | Cost-optimized control node where USB host capability and high I/O count are unnecessary | Choose for space-constrained, lower-complexity applications like simple sensor nodes or motor drivers |
Compared with R5F5631ACDLJ#U0, R5F5631BDDLJ#U0 offers +256 KB flash for larger firmware while retaining identical performance and interface set; R5F5630ADFL#U0 trades I/O count, USB OTG, and SRAM for smaller footprint and lower BOM cost - making it suitable for tiered product variants.
Availability
R5F5631ACDLJ#U0 is available at Aetrix Electronics and suitable for industrial control, smart metering, building automation, and medical diagnostic peripherals requiring stable component supply, long-term lifecycle assurance, and automotive-grade traceability.
Supply support for R5F5631ACDLJ#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets.
The RX631 Group is engineered for high-integrity embedded applications demanding real-time determinism, functional safety (IEC 60730), and rich peripheral integration - excluding Ethernet to optimize cost and power for non-networked edge controllers.
FAQ
What is the maximum operating frequency and CPU performance of the R5F5631ACDLJ#U0?
The R5F5631ACDLJ#U0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using its 32-bit RX CPU core. It includes a single-precision IEEE-754 floating-point unit (FPU), 32×32→64-bit hardware multiplier, and 32/32→32-bit divider - enabling efficient execution of control algorithms and signal processing tasks without software emulation overhead in the R5F5631ACDLJ#U0.
Does the R5F5631ACDLJ#U0 include an Ethernet MAC controller?
No, the R5F5631ACDLJ#U0 does not include an Ethernet MAC controller. It belongs to the RX631 Group, which explicitly excludes Ethernet functionality - unlike the RX63N Group. This distinction is confirmed in Renesas documentation (R01DS0098EJ0180), where Table 1.2 shows "Ethernet controller" as "Not available" for all RX631 packages, including the R5F5631ACDLJ#U0's 100-pin TFLGA variant.
What are the memory resources available on the R5F5631ACDLJ#U0?
The R5F5631ACDLJ#U0 integrates 768 KB of on-chip flash memory (no wait states at 100 MHz), 128 KB of SRAM (with deep software standby backup capability), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These resources support robust firmware storage, real-time data buffering, and nonvolatile parameter retention - all verified in the official Renesas datasheet R01DS0098EJ0180 for the R5F5631ACDLJ#U0.
Which communication interfaces are supported by the R5F5631ACDLJ#U0?
The R5F5631ACDLJ#U0 supports USB 2.0 host/function/OTG (full-speed), three CAN 2.0B modules (32 mailboxes each), up to 13 SCI channels (including LIN and smart-card modes), four I²C interfaces (one FM+), and three RSPI channels. It also includes a parallel data capture unit (PDC) and supports IEBus - all documented for the RX631 Group in R01DS0098EJ0180, confirming full interface availability for the R5F5631ACDLJ#U0.
What is the package type and operating temperature range of the R5F5631ACDLJ#U0?
The R5F5631ACDLJ#U0 uses the PTLG0100JA-A package: a 100-pin Thin Fine-Pitch Land Grid Array measuring 7 × 7 mm with 0.65 mm pitch. It is rated for industrial operation from -40°C to +85°C (D version), as specified in Table 1.3 of R01DS0098EJ0180 and confirmed across all RX631 100-pin TFLGA variants including the R5F5631ACDLJ#U0.
R5F5631ACDLJ#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 14x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631ACDLJ#U0 FAQ
1.How can I place an order for R5F5631ACDLJ#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631ACDLJ#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631ACDLJ#U0 reliable?
The price and inventory of R5F5631ACDLJ#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631ACDLJ#U0 is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631ACDLJ#U0 transactions.
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R5F5631ACDLJ#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631ACDLJ#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631ACDLJ#U0?
For technical support, including R5F5631ACDLJ#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631ACDLJ#U0 requirements.
6.How does Aetrix verify that R5F5631ACDLJ#U0 is sourced from the original manufacturer or authorized distributors?
All R5F5631ACDLJ#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631ACDLJ#U0 meets industry standards.
7.What is the process for return or replacement of R5F5631ACDLJ#U0?
All R5F5631ACDLJ#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631ACDLJ#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631ACDLJ#U0 part is unused and in its original packaging.
Return procedure for R5F5631ACDLJ#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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