Renesas R5F5631ADDBG#U0

Overview

R5F5631ADDBG#U0 from Renesas is a 100-MHz 32-bit RX631 Group MCU with integrated FPU, 768 KB on-chip flash memory, 128 KB SRAM, 32 KB data flash, and full peripheral set excluding Ethernet MAC. It features 12-bit and 10-bit A/D converters (21 + 8 channels), dual 10-bit D/A outputs, RTC with battery backup, USB 2.0 host/function interface, CAN v2.0B (2 channels), 4× I²C, 3× RSPI, 13× SCI, and operates from 2.7–3.6 V at –40 to +85°C in a 176-pin LFBGA package.

For engineers reviewing the R5F5631ADDBG#U0 datasheet, R5F5631ADDBG#U0 pinout, R5F5631ADDBG#U0 application, or R5F5631ADDBG#U0 equivalent, key selection criteria include its RX631 Group identity (no Ethernet), 768 KB flash/128 KB RAM configuration, PLBG0176GA-A 13 × 13 mm 0.8-mm pitch package, CAN + USB + multiple serial interfaces, and industrial temperature grade - all critical for embedded control, HMI, and industrial automation designs requiring deterministic real-time performance without Ethernet PHY dependency.

Technical Context

The R5F5631ADDBG#U0 implements the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions, delivering 165 DMIPS at 100 MHz. It integrates single-precision IEEE-754 FPU, memory protection unit (MPU), and JTAG/FINE debugging interfaces.

Its peripheral subsystem includes MTU2 (6-channel 16-bit timer), TPU (12-channel 16-bit timer), 8-bit TMR, CMT, RTC with time-capture, IWDT, 12-bit S12AD (21 ch), 10-bit AD (8 ch), DA (2 ch), DEU AES engine, CRC calculator, and parallel data capture unit - all clocked via configurable PCLK up to 50 MHz.

Key Specifications

Pinout & Package

Package: PLBG0176GA-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array, 13 × 13 mm body, 0.8 mm ball pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with R5F563NACDBG#U0, R5F5631ADDBG#U0 removes Ethernet hardware to lower cost and power, while retaining identical flash/RAM and package - ideal when network connectivity is handled externally. Against R5F566TEADFP#U0, it trades higher CPU speed and motor-specific peripherals for greater serial interface density and larger SRAM, favoring protocol gateway and HMI roles.

Availability

R5F5631ADDBG#U0 is available at Aetrix Electronics and suitable for industrial automation, smart metering, and human-machine interface applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant LFBGA packaging.

Supply support for R5F5631ADDBG#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.

The RX631 Group is designed for cost-optimized, high-integration industrial control applications - emphasizing rich serial connectivity, deterministic real-time performance, and functional safety readiness without Ethernet MAC overhead.

FAQ

What is the maximum operating frequency and core architecture of the R5F5631ADDBG#U0?

The R5F5631ADDBG#U0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instruction set. It delivers 165 DMIPS and includes single-precision IEEE-754 floating-point unit, multiplier (1-cycle), and divider (2-cycle) - enabling high-efficiency deterministic execution for real-time embedded applications without external math acceleration.

Does the R5F5631ADDBG#U0 include an Ethernet MAC controller?

No, the R5F5631ADDBG#U0 belongs to the RX631 Group, which explicitly excludes the Ethernet MAC and associated EDMAC peripherals. This distinguishes it from the RX63N Group (e.g., R5F563NACDBG#U0). The R5F5631ADDBG#U0 retains full USB 2.0 host/function, CAN, I²C, RSPI, and SCI interfaces - making it suitable for applications where wired Ethernet is implemented externally or not required.

What memory resources are integrated into the R5F5631ADDBG#U0?

The R5F5631ADDBG#U0 integrates 768 KB of on-chip flash memory (zero-wait access at 100 MHz), 128 KB of SRAM (zero-wait), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. All memory blocks support background operation, allowing concurrent code execution and data flash updates - critical for field-upgradable industrial firmware deployed in the R5F5631ADDBG#U0.

Which analog peripherals are available on the R5F5631ADDBG#U0?

The R5F5631ADDBG#U0 includes a 12-bit A/D converter with 21 input channels and sample-and-hold, a separate 10-bit A/D converter with 8 channels, two 10-bit D/A converters, an on-chip temperature sensor (±1°C accuracy), and a CRC calculator. These analog resources support precision sensor interfacing, closed-loop control, and metrology functions - all directly usable by application firmware without external signal conditioning in the R5F5631ADDBG#U0.

What package type and pin count does the R5F5631ADDBG#U0 use?

The R5F5631ADDBG#U0 uses the PLBG0176GA-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array with 13 × 13 mm body size and 0.8 mm ball pitch. This RoHS-compliant, lead-free LFBGA package provides 133 GPIO pins (18 of which are 5-V tolerant), dedicated power/ground balls per I/O bank, and thermal pad compatibility - optimized for industrial PCB layouts requiring high-density interconnect and thermal reliability in the R5F5631ADDBG#U0.