Renesas R5F5631BDDFB#V0
- Part No.:
- R5F5631BDDFB#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5631BDDFB#V0.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631BDDFB#V0 from Renesas is a 100 MHz 32-bit RX631 Group microcontroller with integrated FPU, 1 MB on-chip flash memory, 128 KB SRAM, and full-featured peripheral set excluding Ethernet MAC. It features 12-bit and 10-bit A/D converters (21/8 channels), dual 10-bit D/A outputs, CAN v2.0B (2 channels), USB 2.0 full-speed host/function, and operates from 2.7–3.6 V in industrial temperature range (−40 to +85°C). It targets embedded control in industrial HMIs and networked sensor nodes.
For engineers reviewing the R5F5631BDDFB#V0 datasheet, R5F5631BDDFB#V0 pinout, R5F5631BDDFB#V0 application, or R5F5631BDDFB#V0 equivalent, key selection criteria include its 144-pin LQFP package, absence of Ethernet controller (distinguishing it from RX63N), support for USB OTG and CAN, real-time clock with battery backup, and IEC60730-compliant safety functions including CRC and self-diagnostic A/D.
Technical Context
The R5F5631BDDFB#V0 implements the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling 165 DMIPS at 100 MHz. It integrates single-precision IEEE-754 FPU, memory protection unit (MPU), and JTAG/FINE debug interfaces.
Its peripheral subsystem includes three SCI modules supporting asynchronous, SPI-like, and I²C-like modes; four I²C bus interfaces (one FM+); three RSPI channels; two CAN controllers (32 mailboxes each); and dedicated DMA controllers (DMAC, EXDMAC, DTC) for offloading data movement from CPU during high-throughput operations like USB or serial transfers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC with 5-stage pipeline, 100 MHz max operation, 165 DMIPS performance |
| Flash Memory | 1 MB on-chip main flash, zero-wait-state access at 100 MHz, programmable in-system |
| SRAM | 128 KB on-chip SRAM, zero-wait-state access, supports deep software standby backup |
| A/D Converter | 21-channel 12-bit S12AD + 8-channel 10-bit AD, 1.0 µs conversion time at 50 MHz PCLK |
| D/A Converter | 2-channel 10-bit DA output, voltage range 0 V to VREFH, independent reference support |
| Communication | USB 2.0 full-speed host/function/OTG (1 port), CAN v2.0B (2 modules, 32 mailboxes each), 4× I²C (1× FM+), 13× SCI, 3× RSPI |
| Package & Temp | 144-pin LQFP (PLQP0144KA-A, 20 × 20 mm, 0.5 mm pitch), −40 to +85°C operating range (D version) |
Pinout & Package
Package: PLQP0144KA-A - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.5 mm lead pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Core and I/O power pins distributed across multiple locations for noise reduction and current sharing |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables precise system clock generation and PLL multiplication |
| USB_VBUS / USB_DP / USB_DM | USB power detection and differential data lines | Enables host/device mode detection and full-speed USB 2.0 communication without external transceiver |
| TXDn / RXDn (SCI) | Asynchronous serial transmit/receive | Up to 13 SCI channels configurable per pin; supports baud rates up to 15 Mbps with fractional dividers |
| TXDn / RXDn / RTSn / CTSn (USB) | USB function/host control signals | Direct interface to USB PHY; supports OTG ID detection and session request protocol (SRP) |
| CRX0 / CTX0 (CAN) | CAN transceiver differential inputs/outputs | Direct connection to external CAN transceiver; supports ISO 11898-1 standard frames and error handling |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware acceleration enables real-time motor control and sensor fusion algorithms |
| IEC60730 safety support | Integrated oscillation-stop detection, CRC calculator, IWDT, and A/D self-diagnostic reduce functional safety certification effort |
| Flexible clock system | Multiple on-chip oscillators (LOCO, HOCO), PLL, and independent clock domains (ICLK/PCLK/FCLK/BCLK) simplify power/performance tuning |
| Low-power operation | Four low-power modes (Sleep, All-module stop, Software standby, Deep software standby); 500 µA/MHz active current |
| Secure data handling | Data Encryption Unit (DEU) with AES-128/192/256 in ECB/CBC modes protects firmware and sensitive data |
Applications
| Industrial HMI Controller | Smart Sensor Node |
|---|---|
|
Use Scenario: Standalone panel-mounted display with touch interface, local logic, and fieldbus connectivity. IC Role / Device Role / Timing Role: Main application processor executing GUI rendering, real-time control loop, and CAN/USB device stack. Use Value: Integrated 128 KB SRAM eliminates external RAM; USB OTG enables field firmware updates via thumb drive; RTC with battery backup maintains timestamp integrity during power loss. |
Use Scenario: Battery-powered environmental monitor collecting temperature, humidity, and analog sensor data for edge preprocessing. IC Role / Device Role / Timing Role: Central data acquisition and processing unit managing multi-channel A/D sampling, CRC-verified storage, and low-power wake-up scheduling. Use Value: 1.0 µs A/D conversion enables high-resolution sampling at 1 MSPS; deep software standby draws sub-µA current; internal temperature sensor provides on-die calibration reference. |
| Programmable Logic Controller (PLC) I/O Module | USB-Capable Industrial Gateway |
|
Use Scenario: DIN-rail mounted digital I/O expansion module with isolated inputs/outputs and CAN backbone interface. IC Role / Device Role / Timing Role: Real-time I/O scheduler and CAN message handler with deterministic interrupt latency and register write protection. Use Value: MPU enforces memory isolation between firmware and user logic; 133 GPIOs (111 usable in 144-pin package) support flexible I/O mapping; TPU/MTU2 timers enable precise PWM and encoder counting. |
Use Scenario: Protocol translator bridging Modbus RTU over RS485 to USB HID or CDC ACM for PC-based SCADA integration. IC Role / Device Role / Timing Role: Dual-role USB controller acting as CDC ACM device or host for USB-to-serial adapters, with simultaneous CAN and SCI operation. Use Value: Single-chip solution replaces discrete USB bridge + MCU; USB buffer RAM (2 KB) handles bulk transfers without CPU intervention; RSPI and SCI coexist with USB traffic via DTC-assisted DMA. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDFB#V0 | Same 144-pin LQFP package, but RX63N Group: adds Ethernet MAC (10/100 Mbps), removes sub-clock oscillator, increases flash to 2 MB | Required where LAN connectivity is mandatory (e.g., industrial Ethernet gateways); not suitable if Ethernet is unused and cost/power must be minimized | Select R5F563NEDDFB#V0 only when Ethernet interface is essential; otherwise R5F5631BDDFB#V0 offers lower BOM cost and reduced layout complexity |
| R5F566TADDFB#V0 | RX66T Group part: higher 160 MHz CPU, enhanced timer resolution (32-bit MTU3), no DEU or IEC60730 features, same 144-pin LQFP | Better suited for high-performance motor control (e.g., servo drives) but lacks safety-certifiable peripherals and crypto acceleration | Choose R5F566TADDFB#V0 for compute-intensive motion control; retain R5F5631BDDFB#V0 when functional safety, USB OTG, or AES encryption are required |
Compared with R5F563NEDDFB#V0, the R5F5631BDDFB#V0 omits Ethernet to reduce cost and power while retaining USB OTG and CAN-ideal for non-LAN edge nodes. Against R5F566TADDFB#V0, it trades raw speed for certified safety features and cryptographic capability, making it preferable for regulated industrial equipment.
Availability
R5F5631BDDFB#V0 is available at Aetrix Electronics and suitable for industrial HMIs, smart sensor nodes, PLC I/O modules, and USB-capable industrial gateways requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F5631BDDFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is designed for cost-sensitive, safety-aware industrial control applications-emphasizing IEC60730 compliance, robust communication (CAN/USB), and low-power operation without Ethernet overhead.
FAQ
What is the maximum operating frequency and CPU performance of the R5F5631BDDFB#V0?
The R5F5631BDDFB#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using the 32-bit RX CPU core. Its 5-stage pipeline, variable-length instruction set, and integrated single-precision IEEE-754 FPU enable efficient execution of real-time control and signal processing tasks. This performance level is confirmed in Renesas document R01DS0098EJ0180.
Does the R5F5631BDDFB#V0 include an Ethernet controller?
No, the R5F5631BDDFB#V0 does not include an Ethernet controller. It belongs to the RX631 Group, which explicitly excludes the ETHERC module present in the RX63N Group. This distinction is documented in Table 1.2 of R01DS0098EJ0180, confirming Ethernet availability only for RX63N variants such as R5F563NEDDFB#V0.
What are the memory resources available on the R5F5631BDDFB#V0?
The R5F5631BDDFB#V0 integrates 1 MB of on-chip flash memory (zero-wait-state at 100 MHz), 128 KB of SRAM (also zero-wait-state), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These memory resources are specified in Table 1.3 of R01DS0098EJ0180 under the RX631 Group entries for 144-pin LQFP packages.
Which communication interfaces does the R5F5631BDDFB#V0 support?
The R5F5631BDDFB#V0 supports USB 2.0 full-speed host/function/OTG (1 port), two CAN v2.0B modules (32 mailboxes each), four I²C interfaces (including one FM+), 13 SCI channels, and three RSPI channels. It lacks Ethernet but retains comprehensive serial and fieldbus connectivity suitable for industrial edge devices.
Is the R5F5631BDDFB#V0 qualified for functional safety standards?
Yes, the R5F5631BDDFB#V0 includes hardware features aligned with IEC60730 Class B requirements: oscillation-stop detection, CRC calculator (with three polynomials), independent watchdog timer (IWDT), and self-diagnostic capability for the 10-bit A/D converter. These are explicitly listed in the "Useful functions for IEC60730 compliance" section of R01DS0098EJ0180.
R5F5631BDDFB#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631BDDFB#V0 FAQ
1.How can I place an order for R5F5631BDDFB#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631BDDFB#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631BDDFB#V0 reliable?
The price and inventory of R5F5631BDDFB#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631BDDFB#V0 is usually 5 days.
3.What payment methods are accepted for R5F5631BDDFB#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631BDDFB#V0 transactions.
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R5F5631BDDFB#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631BDDFB#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631BDDFB#V0?
For technical support, including R5F5631BDDFB#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631BDDFB#V0 requirements.
6.How does Aetrix verify that R5F5631BDDFB#V0 is sourced from the original manufacturer or authorized distributors?
All R5F5631BDDFB#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631BDDFB#V0 meets industry standards.
7.What is the process for return or replacement of R5F5631BDDFB#V0?
All R5F5631BDDFB#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631BDDFB#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631BDDFB#V0 part is unused and in its original packaging.
Return procedure for R5F5631BDDFB#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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