Renesas R5F5631EDDBG#G0
- Part No.:
- R5F5631EDDBG#G0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F5631EDDBG#G0.pdf
- Description:
- RX631 2MB/128KB 176BGA CAN 100MH
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631EDDBG#G0 from Renesas is a 100 MHz, 32-bit RX CPU core microcontroller in the RX631 Group, featuring 2 MB on-chip flash memory, 128 KB SRAM, 32 KB data flash, single-precision IEEE-754 FPU, and integrated 12-bit/10-bit A/D converters. It operates from a 2.7–3.6 V supply, supports four low-power modes, and targets industrial control and networked embedded systems requiring deterministic real-time performance without Ethernet.
For engineers reviewing the R5F5631EDDBG#G0 datasheet, R5F5631EDDBG#G0 pinout, R5F5631EDDBG#G0 application, or R5F5631EDDBG#G0 equivalent, key selection criteria include its 176-pin LFBGA (PLBG0176GA-A) package, -40 to +105°C extended temperature grade (G version), absence of Ethernet MAC (distinguishing it from RX63N), and support for USB 2.0 host/function, CAN v2.0B (3 channels), and up to 13 SCI interfaces.
Technical Context
The R5F5631EDDBG#G0 implements the CISC Harvard-architecture RX CPU with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU). It executes at 165 DMIPS @ 100 MHz and integrates dual multiply-and-accumulate units plus a 32-bit hardware multiplier completing operations in one cycle.
Its peripheral set includes MTU2 (6-channel 16-bit timer), TPU (12-channel 16-bit timer), 8-bit TMR, 4-channel compare-match timers, RTC with battery backup, independent watchdog (IWDT), and DEU AES encryption engine supporting 128/192/256-bit keys in ECB/CBC modes - all synchronized to configurable PCLK, ICLK, and BCLK domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard architecture with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK), enabling deterministic real-time execution |
| Flash Memory | 2 Mbytes on-chip main flash, zero-wait-state access at 100 MHz |
| RAM | 128 Kbytes on-chip SRAM, no-wait access for both instructions and operands |
| A/D Converters | 21-channel 12-bit S12AD + 8-channel 10-bit AD, 1.0 μs conversion time @ 50 MHz PCLK |
| Communication Interfaces | USB 2.0 host/function/OTG (full-speed), CAN v2.0B (3 modules, 32 mailboxes each), 13 SCI, 4 RIIC (1 Mbps), 3 RSPI |
| Operating Temperature | -40°C to +105°C (G version), qualified for extended industrial environments |
| Supply Voltage | 2.7 V to 3.6 V (VCC/AVCC0/VREFH/VCC_USB), 2.3 V min for RTC backup (VBATT) |
Pinout & Package
Package: 176-pin LFBGA (PLBG0176GA-A), 13 × 13 mm, 0.8 mm pitch, RoHS-compliant, thermal pad exposed on underside.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated power/ground pairs per I/O bank; decoupling required per Renesas layout guidelines |
| P00–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P90–P97, PA0–PA7, PB0–PB7, PC0–PC7, PD0–PD7, PE0–PE7, PF0–PF7, PG0–PG7, PH0–PH7, PJ0–PJ7, PK0–PK7, PL0–PL7, PM0–PM7, PN0–PN7, PP0–PP7, PQ0–PQ7, PR0–PR7, PS0–PS7, PT0–PT7, PU0–PU7, PV0–PV7, PW0–PW7, PX0–PX7, PY0–PY7, PZ0–PZ7 | General-purpose I/O ports | 133 total I/O pins; 5-V tolerant on 18 pins; open-drain, pull-up, and drive-strength configurable |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; internal PLL generates 100 MHz ICLK |
| RTC_XTAL / RTC_EXTAL | Sub-clock oscillator input/output | Enables battery-backed RTC operation down to 2.3 V VBATT |
| RES# | Active-low reset input | Asynchronous reset pin; compatible with external reset ICs and power-on reset circuits |
| MD0 / MD1 | Mode selection inputs | Configure boot mode (ROM/flash/external bus); sampled at power-on reset |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision 32-bit hardware accelerator, enabling efficient math-intensive control algorithms |
| Data Encryption Unit (DEU) | AES-128/192/256 encryption/decryption in ECB/CBC modes, supporting secure firmware updates and data confidentiality |
| Real-time clock (RTC) | Calendar/clock with alarm, periodic interrupt, carry interrupt, and time-capture on external event signals |
| Low-power operation | Four distinct low-power modes (sleep, all-module clock stop, software standby, deep software standby) with sub-μA retention |
| On-chip debugging | JTAG and FINE two-wire interfaces supported; compatible with E1/E20 emulators for non-intrusive real-time debug |
| IEC 60730 compliance support | Integrated oscillation-stop detection, CRC calculator, self-diagnostic A/D, IWDT, and frequency measurement for Class B safety |
Applications
| Industrial PLC Controller | Smart Energy Meter |
|---|---|
Use Scenario: Real-time logic execution, analog sensor acquisition (voltage/current), and serial communication with utility backhaul modems. IC Role / Device Role / Timing Role: Main application processor executing ladder logic, managing 21-channel 12-bit A/D sampling, and driving RS485/SCI-based DLMS/COSEM protocol stacks. Use Value: Deterministic 100 MHz timing ensures sub-millisecond scan cycles; integrated DEU secures firmware and metering data against tampering. |
Use Scenario: High-accuracy energy measurement with harmonic analysis, tamper detection, and secure over-the-air firmware updates. IC Role / Device Role / Timing Role: System controller interfacing with metrology ADCs, managing RTC-critical billing intervals, and executing AES-encrypted OTA update verification. Use Value: 12-bit A/D with sample-and-hold enables simultaneous voltage/current sampling; -40°C to +105°C rating ensures reliability in outdoor meter enclosures. |
| Factory Automation HMI | Building Management Controller |
Use Scenario: Local human-machine interface with touch panel, LED indicators, and fieldbus connectivity (CAN/RS485) to PLCs and sensors. IC Role / Device Role / Timing Role: Central MCU handling GUI rendering via parallel interface, processing touch interrupts, and managing multi-protocol fieldbus gateways. Use Value: 133 GPIOs support direct LED/button matrix control; USB host capability enables configuration via USB flash drives. |
Use Scenario: Distributed HVAC controller acquiring temperature/humidity, driving valve actuators, and communicating via BACnet MS/TP or Modbus RTU. IC Role / Device Role / Timing Role: Real-time scheduler coordinating 10-bit A/D readings, PWM fan control, and deterministic SCI-based fieldbus messaging. Use Value: Integrated MTU2 and TPU provide precise phase-controlled PWM for EC motors; RTC with battery backup maintains scheduling across power loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDBG#G0 | Same package and pinout; adds Ethernet MAC (10/100 Mbps MII/RMII) and EDMAC; 2 MB flash, 128 KB RAM | Required where wired LAN connectivity, WoL, or IEEE 802.3x flow control is mandatory | Select R5F563NEDDBG#G0 only if Ethernet PHY integration is needed; otherwise R5F5631EDDBG#G0 reduces BOM cost and layout complexity |
| R5F566TEBDFP#30 | RX66T Group; 160 MHz CPU, 2 MB flash, 384 KB RAM, enhanced MTU3 timers, no DEU, same 100-pin LQFP footprint | Targeted at motor control with advanced PWM synchronization and encoder interfaces | Choose R5F566TEBDFP#30 for servo/inverter applications needing higher PWM resolution and faster computation; not drop-in compatible |
Compared with R5F563NEDDBG#G0, the R5F5631EDDBG#G0 removes Ethernet hardware to reduce power and cost while retaining identical USB/CAN/SCI peripherals and extended temperature support; versus R5F566TEBDFP#30, it trades higher clock speed and motor-control features for broader general-purpose peripheral coverage and integrated security.
Availability
R5F5631EDDBG#G0 is available at Aetrix Electronics and suitable for industrial automation, smart metering, and building management systems requiring stable component supply, extended temperature operation, and long-term lifecycle assurance.
Supply support for R5F5631EDDBG#G0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is designed for high-performance, safety-aware industrial control applications, emphasizing real-time determinism, functional safety (IEC 60730), and secure firmware execution - with R5F5631EDDBG#G0 delivering this capability in an extended-temperature LFBGA package.
FAQ
What is the maximum operating frequency and CPU performance of the R5F5631EDDBG#G0?
The R5F5631EDDBG#G0 operates at a maximum system clock frequency of 100 MHz and delivers 165 DMIPS of computational performance. Its RX CPU core includes a hardware 32-bit multiplier (one-cycle execution), divider (two-cycle execution), and single-precision IEEE-754 floating-point unit - all verified in Renesas' R01DS0098EJ0180 datasheet Rev.1.80.
Does the R5F5631EDDBG#G0 include an Ethernet MAC controller?
No, the R5F5631EDDBG#G0 belongs to the RX631 Group and does not integrate an Ethernet MAC or EDMAC. This distinguishes it from the RX63N Group (e.g., R5F563NEDDBG#G0). The R5F5631EDDBG#G0 retains full USB 2.0 host/function/OTG, CAN v2.0B (3 channels), and 13 SCI interfaces for alternative wired connectivity.
What package type and pin count does the R5F5631EDDBG#G0 use?
The R5F5631EDDBG#G0 uses a 176-pin LFBGA package (PLBG0176GA-A), measuring 13 × 13 mm with 0.8 mm pitch and an exposed thermal pad. It provides 133 general-purpose I/O pins, 18 of which are 5-V tolerant, and supports configurable drive strength, pull-up, and open-drain operation per Renesas' package documentation.
What memory resources are integrated into the R5F5631EDDBG#G0?
The R5F5631EDDBG#G0 integrates 2 Mbytes of on-chip flash memory (zero-wait-state at 100 MHz), 128 Kbytes of SRAM (no-wait access), and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles. All memory blocks support background programming/erasing and are protected by register write-protection mechanisms.
Is the R5F5631EDDBG#G0 qualified for extended temperature operation?
Yes, the R5F5631EDDBG#G0 is the "G version" and is qualified for operation from -40°C to +105°C. This extended temperature range is confirmed in Table 1.3 of the R01DS0098EJ0180 datasheet and applies specifically to the G-suffix part number, making it suitable for demanding industrial and outdoor embedded applications.
R5F5631EDDBG#G0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX631
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631EDDBG#G0 FAQ
1.How can I place an order for R5F5631EDDBG#G0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631EDDBG#G0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631EDDBG#G0 reliable?
The price and inventory of R5F5631EDDBG#G0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631EDDBG#G0 is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631EDDBG#G0 transactions.
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R5F5631EDDBG#G0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631EDDBG#G0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631EDDBG#G0?
For technical support, including R5F5631EDDBG#G0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631EDDBG#G0 requirements.
6.How does Aetrix verify that R5F5631EDDBG#G0 is sourced from the original manufacturer or authorized distributors?
All R5F5631EDDBG#G0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631EDDBG#G0 meets industry standards.
7.What is the process for return or replacement of R5F5631EDDBG#G0?
All R5F5631EDDBG#G0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631EDDBG#G0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631EDDBG#G0 part is unused and in its original packaging.
Return procedure for R5F5631EDDBG#G0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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