Renesas R5F5631EDDFB#11
- Part No.:
- R5F5631EDDFB#11
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5631EDDFB#11.pdf
- Description:
- 32BIT MCU RX631 2M LQFP144 -40/+
- Quantity:
- Payment:

- Shipping:

Inventory:4,425
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5631EDDFB#11 from Renesas is a 100 MHz 32-bit RX631 Group microcontroller featuring a single-precision IEEE-754 FPU, 2 MB on-chip flash memory, 128 KB SRAM, and integrated 10-/12-bit A/D converters. It supports USB 2.0 full-speed host/function/OTG, CAN (ISO 11898-1), up to 13 SCI channels, and operates from a 2.7–3.6 V supply across –40 to +85°C. It targets industrial control and connected HMI applications requiring deterministic real-time performance without Ethernet.
For engineers reviewing the R5F5631EDDFB#11 datasheet, R5F5631EDDFB#11 pinout, R5F5631EDDFB#11 application, or R5F5631EDDFB#11 equivalent, key selection criteria include its 176-pin LQFP package, absence of Ethernet MAC (distinguishing it from RX63N), support for 100-MHz operation with MPU and FPU, and compatibility with Renesas E1/E20 debug interfaces.
Technical Context
The R5F5631EDDFB#11 implements the RXv1 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a memory protection unit (MPU), JTAG/FINE debugging, and dual-clock domain operation - system clock (ICLK) up to 100 MHz and peripheral clock (PCLK) up to 50 MHz - enabling precise timing isolation for real-time peripherals.
Its peripheral set includes three CAN modules (32 mailboxes each), four I²C interfaces (one FM+), three RSPI channels, and a parallel data capture unit (PDC) supporting image sensor interfacing. The device lacks Ethernet MAC and SDRAM controller - confirmed exclusions for RX631 Group - and omits sub-clock oscillator for RTC battery backup, distinguishing it from RX63N variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC core with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK); enables deterministic real-time execution |
| Flash Memory | 2 MB on-chip main flash, zero-wait-state access at 100 MHz |
| SRAM | 128 KB on-chip SRAM, zero-wait-state access for instruction/operand storage |
| A/D Converters | 21-channel 12-bit S12AD + 8-channel 10-bit AD; 1.0 µs conversion time @ 50 MHz PCLK |
| D/A Converters | 2-channel 10-bit DA output, voltage range 0 V to VREFH |
| Operating Voltage | 2.7–3.6 V (VCC/AVCC0/VREFH/VCC_USB); supports single-supply industrial systems |
| Temperature Range | –40°C to +85°C (D version); qualified for industrial ambient conditions |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 × 24 mm, 0.5 mm pitch, RoHS-compliant, surface-mount.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, VREFH | Power supply inputs | Separate analog/digital power domains; VREFH sets A/D reference voltage |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 4–16 MHz external crystal for precise system clock generation |
| RESET | Active-low reset input | Asynchronous hardware reset; triggers POR, LVD, and software-initiated resets |
| MD0, MD1 | Mode select pins | Configure boot mode (single-chip, ROM-enabled/disabled expansion) |
| IRQ0–IRQ15 | External interrupt inputs | 16 dedicated edge-triggered interrupt request lines for fast event response |
| USB_VBUS, USB_ID | USB OTG interface signals | Enable host/device role detection and VBUS monitoring per USB 2.0 specification |
| TXD0–TXD12, RXD0–RXD12 | SCI serial data I/O | 13 independent SCI channels support asynchronous, SPI/I²C emulation, LIN, and smart-card modes |
| TXD0–TXD2, RXD0–RXD2 | RSPI master/slave I/O | Three full-duplex RSPI ports with configurable bit length (8–32 bits) and double-buffered transfer |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | Single-precision IEEE-754 compliant; accelerates motor control, filtering, and sensor fusion math |
| Memory Protection Unit (MPU) | Enforces privilege-level memory access boundaries; critical for IEC 60730 Class B compliance |
| Data Encryption Unit (DEU) | AES-128/192/256 encryption/decryption in ECB/CBC modes; secures firmware updates and data |
| Real-time peripherals | MTU2 (6-channel), TPU (12-channel), CMT (4-channel), and RTC with alarm/carry interrupts |
| Low-power operation | Four low-power modes (Sleep, All-module stop, Software standby, Deep software standby); 500 µA/MHz active current |
| Debug & trace | JTAG and two-wire FINE interfaces; supports Renesas E1/E20 emulators for non-intrusive real-time debugging |
Applications
| Industrial PLC I/O Module | Smart Energy Metering Gateway |
|---|---|
|
Use Scenario: Local processing of analog sensor inputs (voltage, current, temperature) and digital I/O control in DIN-rail mounted PLC modules. IC Role / Device Role / Timing Role: Central MCU executing real-time control loops, A/D sampling at ≤1 µs resolution, and CAN-based fieldbus communication. Use Value: Integrated 21-channel 12-bit A/D with sample-and-hold and programmable trigger sources eliminates external ADC, reducing BOM count and layout area. |
Use Scenario: Aggregation and preprocessing of metering data from multiple smart meters via RS485/CAN before upstream transmission. IC Role / Device Role / Timing Role: Protocol gateway MCU handling multi-interface bridging (CAN, SCI, RSPI), secure firmware updates, and RTC-synchronized logging. Use Value: Dual CAN controllers (32 mailboxes each) and AES-256 DEU enable concurrent fieldbus traffic and encrypted OTA updates without external crypto IC. |
| Human-Machine Interface (HMI) Controller | Factory Automation Edge Node |
|
Use Scenario: Touch-enabled display panel with local UI rendering, button scanning, and status LED control in packaging machinery. IC Role / Device Role / Timing Role: Application processor managing graphics buffer, touch interrupt handling, and USB host for peripheral attachment (keyboards, flash drives). Use Value: USB 2.0 full-speed host/function/OTG with 2 KB on-chip RAM buffer allows plug-and-play peripheral support without external memory. |
Use Scenario: Distributed motion controller coordinating stepper/servo drives via pulse-train outputs and encoder feedback in CNC equipment. IC Role / Device Role / Timing Role: Real-time motion sequencer generating synchronized PWM waveforms and capturing quadrature encoder counts with MTU2/TPU. Use Value: MTU2's complementary PWM mode and phase-counting capability deliver precise motor commutation timing with <100 ns jitter tolerance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDFB#11 | Includes Ethernet MAC, RMII/MII interface, and SDRAM controller; same 176-pin LQFP package | Required for network-connected gateways, remote I/O, or web-enabled HMIs needing TCP/IP stack offload | Select when Ethernet connectivity and external memory expansion are mandatory; adds ~$1.20 cost and design complexity |
| R5F562T7DDFB#11 | RX62T Group; 100 MHz, 512 KB flash, 64 KB RAM, no FPU, no DEU, fewer CAN channels (2×) | Suitable for cost-sensitive motor control where floating-point math is handled externally or via software libraries | Choose for simpler, lower-cost motor drive designs without security or high-precision analog requirements |
Compared with R5F5631EDDFB#11, the R5F563NEDDFB#11 adds Ethernet and SDRAM support but increases power and layout footprint, while the R5F562T7DDFB#11 reduces memory, security, and analog capability to meet tighter BOM targets - making the R5F5631EDDFB#11 optimal for balanced industrial control with integrated security and precision sensing.
Availability
R5F5631EDDFB#11 is available at Aetrix Electronics and suitable for industrial PLC I/O modules, smart energy gateways, HMI controllers, and factory automation edge nodes requiring stable component supply, long-term lifecycle assurance, and full Renesas toolchain support.
Supply support for R5F5631EDDFB#11 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is designed for high-performance industrial control applications demanding real-time determinism, functional safety compliance (IEC 60730), and rich analog/motor control peripherals - without Ethernet overhead.
FAQ
What is the maximum operating frequency and core architecture of the R5F5631EDDFB#11?
The R5F5631EDDFB#11 operates at a maximum frequency of 100 MHz using the 32-bit RXv1 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions. It delivers 165 DMIPS and includes a single-precision IEEE-754 floating-point unit. This architecture enables deterministic real-time execution essential for industrial control loops and motor algorithms within the R5F5631EDDFB#11.
Does the R5F5631EDDFB#11 include an Ethernet MAC controller?
No, the R5F5631EDDFB#11 does not include an Ethernet MAC controller. It belongs to the RX631 Group, which explicitly excludes Ethernet functionality - unlike the RX63N Group. This omission reduces silicon area, power consumption, and design complexity for applications that rely on CAN, USB, or serial fieldbuses instead of IP networking. The R5F5631EDDFB#11 retains full USB 2.0 host/function/OTG and triple CAN support.
What are the memory resources available on the R5F5631EDDFB#11?
The R5F5631EDDFB#11 integrates 2 MB of on-chip flash memory with zero-wait-state access at 100 MHz, 128 KB of zero-wait-state SRAM, and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These resources support complex real-time firmware, bootloader partitioning, and secure parameter storage - all without external memory, simplifying PCB layout and improving reliability in the R5F5631EDDFB#11.
Which debug interfaces does the R5F5631EDDFB#11 support?
The R5F5631EDDFB#11 supports both JTAG and two-wire FINE debugging interfaces, compatible with Renesas E1 and E20 emulators. These interfaces enable non-intrusive real-time debugging, flash programming, and trace analysis. The FINE interface reduces pin count and routing complexity compared to full JTAG, making it ideal for space-constrained industrial designs using the R5F5631EDDFB#11.
What peripheral interfaces are included in the R5F5631EDDFB#11 for industrial communication?
The R5F5631EDDFB#11 includes three CAN modules (ISO 11898-1 compliant, 32 mailboxes each), 13 SCI channels supporting asynchronous, SPI/I²C emulation, LIN, and smart-card modes, four I²C interfaces (one FM+), three RSPI ports, and USB 2.0 full-speed host/function/OTG. These interfaces provide robust, multi-protocol fieldbus connectivity - critical for interoperability in industrial networks using the R5F5631EDDFB#11.
R5F5631EDDFB#11 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX631
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631EDDFB#11 FAQ
1.How can I place an order for R5F5631EDDFB#11 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631EDDFB#11 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631EDDFB#11 reliable?
The price and inventory of R5F5631EDDFB#11 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631EDDFB#11 is usually 5 days.
3.What payment methods are accepted for R5F5631EDDFB#11?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631EDDFB#11 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631EDDFB#11?
R5F5631EDDFB#11 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631EDDFB#11 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631EDDFB#11?
For technical support, including R5F5631EDDFB#11 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631EDDFB#11 requirements.
6.How does Aetrix verify that R5F5631EDDFB#11 is sourced from the original manufacturer or authorized distributors?
All R5F5631EDDFB#11 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631EDDFB#11 meets industry standards.
7.What is the process for return or replacement of R5F5631EDDFB#11?
All R5F5631EDDFB#11 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631EDDFB#11, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631EDDFB#11 part is unused and in its original packaging.
Return procedure for R5F5631EDDFB#11:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5631EDDFB#11 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

