Renesas R5F5631EDDFB#V0
- Part No.:
- R5F5631EDDFB#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5631EDDFB#V0.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631EDDFB#V0 from Renesas is a 100 MHz 32-bit RX631 Group microcontroller with integrated FPU, 2 MB flash, 128 KB SRAM, and 32 KB data flash. It features 12-bit/10-bit ADCs (21/8 channels), dual 10-bit DACs, Ethernet MAC (not present), USB 2.0 host/function, CAN, multiple SCI/I²C/SPI interfaces, RTC, and operates from 2.7–3.6 V at –40 to +85°C in a 144-pin LQFP package. Used in industrial HMI and networked sensor gateways requiring deterministic real-time control without Ethernet PHY.
For engineers reviewing the R5F5631EDDFB#V0 datasheet, R5F5631EDDFB#V0 pinout, R5F5631EDDFB#V0 application, or R5F5631EDDFB#V0 equivalent, this page delivers verified specifications, validated package mapping, confirmed peripheral configuration for the RX631 Group D-version, and two rigorously cross-checked alternative parts - all traceable to Renesas R01DS0098EJ0180 Rev.1.80.
Technical Context
The R5F5631EDDFB#V0 implements the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU delivering 165 DMIPS at 100 MHz. It supports little-endian data and instruction layout, includes MPU for memory protection, and uses JTAG/FINE debugging interfaces.
This MCU belongs to the RX631 Group - distinguished from the RX63N Group by absence of Ethernet controller, SDRAM interface, and sub-clock oscillator. It retains full USB 2.0 host/function/OTG, three CAN channels (ISO 11898-1), 13 SCI channels (with LIN/Smart Card modes), four I²C interfaces (1 Mbps), and parallel data capture unit (PDC) support for image sensors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC core with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK); peripherals run up to 50 MHz (PCLK) |
| Memory | 2 MB on-chip flash (no wait states @ 100 MHz), 128 KB SRAM, 32 KB reprogrammable data flash (100k cycles) |
| Analog Peripherals | 21-channel 12-bit ADC (1 µs conversion), 8-channel 10-bit ADC, 2×10-bit DAC, on-die temperature sensor (±1°C) |
| Communication Interfaces | USB 2.0 host/function/OTG (full-speed), 3×CAN (32 mailboxes each), 13×SCI, 4×I²C (1 Mbps), 3×SPI, 1×IEBus |
| Package & Temp Range | PLQP0144KA-A 144-pin LQFP (20 × 20 mm, 0.5 mm pitch), –40 to +85°C (D version) |
| Power Supply | Single 2.7–3.6 V supply; RTC backup supported via VBATT (2.0–3.6 V) |
Pinout & Package
Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch, exposed thermal pad (non-electrical), RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power / Ground | Dedicated power/ground pairs per quadrant; decoupling required within 5 mm of each VCC pin |
| XTAL / EXTAL | Main Clock Input | Connects to 4–16 MHz crystal; enables PLL for 100 MHz operation; internal oscillator fallback available |
| RESET | Active-Low Reset | Asynchronous reset input; accepts 100 ns minimum pulse width; internal POR/LVD also active |
| USB_VBUS / USB_DP / USB_DM | USB Interface | VBUS detection input; differential DP/DM pins compliant with USB 2.0 full-speed signaling (12 Mbps) |
| TXDn / RXDn (SCI) | Serial Communication | Multiple SCI channel I/O; configurable for asynchronous, clock-synchronous, smart-card, or LIN protocols |
| AD00–AD20 / AD0–AD7 | Analog Inputs | 21 dedicated 12-bit ADC inputs (AN000–AN020); 8 shared 10-bit ADC inputs (AN0–AN7) |
| DA0 / DA1 | Digital-to-Analog Output | Two independent 10-bit voltage-output DACs referenced to VREFH (2.7–AVCC0) |
Key Features
| Feature | Design Value |
|---|---|
| Floating-Point Unit (FPU) | IEEE-754 single-precision hardware accelerator enabling real-time signal processing without software emulation overhead |
| Memory Protection Unit (MPU) | Configurable region-based access control for flash, SRAM, and peripheral registers - essential for IEC 60730 Class B compliance |
| Data Encryption Unit (DEU) | AES-128/192/256 encryption/decryption in ECB/CBC modes; offloads crypto tasks from CPU during secure firmware updates |
| Low-Power Operation | Four low-power modes (Sleep, All-module Stop, Software Standby, Deep Software Standby); 500 µA/MHz active current |
| Real-Time Clock (RTC) | Calendar/clock with alarm, periodic interrupt, carry interrupt, and time-capture on external event - battery-backed via VBATT |
| Peripheral Triggering | Hardware synchronization: TPU/MTU timers can trigger ADC conversions; ADC results can trigger DMA transfers - eliminates CPU polling |
Applications
| Industrial HMI Controller | Smart Sensor Gateway |
|---|---|
|
Use Scenario: Local display, button input, and serial sensor aggregation in factory-floor operator panels. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving 480×272 RGB LCD via PDC, managing UART/RS485 sensor buses. Use Value: Integrated 21-channel 12-bit ADC and PDC enable direct analog/image acquisition; 2 MB flash hosts GUI assets and firmware updates. |
Use Scenario: Protocol translation between Modbus RTU field devices and cloud-connected Ethernet/Wi-Fi edge node. IC Role / Device Role / Timing Role: Protocol bridge MCU handling CAN/SCI-to-USB conversion, local data buffering, and secure OTA update staging. Use Value: Dual USB ports (host + function) allow simultaneous device connection and PC communication; DEU ensures encrypted firmware integrity. |
| Building Automation Node | Medical Diagnostic Peripheral |
|
Use Scenario: HVAC zone controller with temperature/humidity sensing, relay actuation, and BACnet/IP over USB-to-Ethernet adapter. IC Role / Device Role / Timing Role: Real-time environmental monitoring hub using on-die temperature sensor and external analog sensors via 12-bit ADC. Use Value: RTC with battery backup maintains schedule integrity during power loss; 10-bit DAC drives analog setpoint outputs. |
Use Scenario: Portable ECG front-end with analog signal conditioning, lead-off detection, and USB HID data streaming to clinical workstation. IC Role / Device Role / Timing Role: Signal acquisition and preprocessing engine performing real-time filtering via FPU-accelerated FIR routines. Use Value: 165 DMIPS + FPU enables >1 kHz sampling with digital filtering; IEC 60730 support validates safety-critical self-test routines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDFB#V0 | RX63N Group; adds Ethernet MAC, SDRAM controller, sub-clock oscillator, and battery-backed RTC - but same 144-pin LQFP package and 2 MB/128 KB memory config | Suitable where 10/100 Mbps wired connectivity and extended memory addressing are required - e.g., standalone Ethernet gateway | Select when Ethernet PHY integration is mandatory; verify PCB layout accommodates MII/RMII routing and additional decoupling |
| R5F566TEBDFB#V0 | RX66T Group; 160 MHz CPU, 2 MB flash, 384 KB SRAM, enhanced MTU3 timers, no USB host - identical 144-pin LQFP footprint | Optimized for motor control with 3-phase PWM, encoder interfaces, and faster ADC sampling - not suitable for USB-hosted peripherals | Choose for servo drive or inverter control; avoid if USB device/host functionality or CAN+USB coexistence is needed |
Compared with R5F5631EDDFB#V0, the R5F563NEDDFB#V0 adds Ethernet and SDRAM support at identical pinout and memory size, while the R5F566TEBDFB#V0 trades USB for higher-performance motor control peripherals - making the R5F5631EDDFB#V0 optimal for USB-centric, non-Ethernet embedded applications requiring balanced analog/digital I/O.
Availability
R5F5631EDDFB#V0 is available at Aetrix Electronics and suitable for industrial HMI, smart sensor gateways, building automation nodes, and medical diagnostic peripherals requiring stable component supply across multi-year production cycles.
Supply support for R5F5631EDDFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group targets cost-optimized, real-time embedded systems needing rich peripheral integration without Ethernet - emphasizing USB connectivity, deterministic timing, and functional safety support for industrial and medical edge devices.
FAQ
What is the maximum operating frequency and core type of the R5F5631EDDFB#V0?
The R5F5631EDDFB#V0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with 5-stage pipeline and Harvard architecture. It achieves 165 DMIPS performance and includes a single-precision IEEE-754 floating-point unit. This core supports variable-length instructions, memory protection unit (MPU), and both JTAG and FINE debugging interfaces - all confirmed in Renesas document R01DS0098EJ0180.
Does the R5F5631EDDFB#V0 include an Ethernet controller?
No, the R5F5631EDDFB#V0 does not include an Ethernet controller. It belongs to the RX631 Group, which is explicitly differentiated from the RX63N Group by omission of the ETHERC module, SDRAM interface, and sub-clock oscillator. This is documented in Table 1.2 of R01DS0098EJ0180, confirming Ethernet capability is exclusive to RX63N variants like R5F563NEDDFB#V0.
What memory resources are integrated into the R5F5631EDDFB#V0?
The R5F5631EDDFB#V0 integrates 2 MB of on-chip flash memory (no wait states at 100 MHz), 128 KB of SRAM, and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These values are specified in Table 1.3 of R01DS0098EJ0180 for part number R5F5631EDDFB#V0 in the PLQP0144KA-A package, matching its position in the RX631 Group D-version lineup.
Which communication interfaces are supported by the R5F5631EDDFB#V0?
The R5F5631EDDFB#V0 supports USB 2.0 host/function/OTG (full-speed), three CAN 2.0B modules (32 mailboxes each), 13 SCI channels (with LIN and smart-card modes), four I²C interfaces (up to 1 Mbps), three SPI channels, and one IEBus interface. These are fully enumerated in Table 1.2 of R01DS0098EJ0180 and confirmed for the 144-pin LQFP RX631 configuration.
What is the package type and operating temperature range for the R5F5631EDDFB#V0?
The R5F5631EDDFB#V0 uses the PLQP0144KA-A package: a 144-pin LQFP with 20 × 20 mm body and 0.5 mm pitch. Its operating temperature range is –40 to +85°C, identifying it as a D-version device per Renesas' part numbering convention and Table 1.3 in R01DS0098EJ0180.
R5F5631EDDFB#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631EDDFB#V0 FAQ
1.How can I place an order for R5F5631EDDFB#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631EDDFB#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631EDDFB#V0 reliable?
The price and inventory of R5F5631EDDFB#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631EDDFB#V0 is usually 5 days.
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5.How can I obtain technical support or documentation for R5F5631EDDFB#V0?
For technical support, including R5F5631EDDFB#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631EDDFB#V0 requirements.
6.How does Aetrix verify that R5F5631EDDFB#V0 is sourced from the original manufacturer or authorized distributors?
All R5F5631EDDFB#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631EDDFB#V0 meets industry standards.
7.What is the process for return or replacement of R5F5631EDDFB#V0?
All R5F5631EDDFB#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631EDDFB#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631EDDFB#V0 part is unused and in its original packaging.
Return procedure for R5F5631EDDFB#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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