Renesas R5F5631EDDLC#U0
- Part No.:
- R5F5631EDDLC#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F5631EDDLC#U0.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 177TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,524
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5631EDDLC#U0 from Renesas is a 100 MHz 32-bit RX CPU-based microcontroller in the RX631 Group, featuring 2 MB on-chip flash memory, 128 KB SRAM, 32 KB data flash, IEEE-754 single-precision FPU, and integrated 10-/12-bit A/D converters - designed for industrial control systems requiring deterministic real-time response and functional safety support (IEC60730).
For engineers reviewing the R5F5631EDDLC#U0 datasheet, R5F5631EDDLC#U0 pinout, R5F5631EDDLC#U0 application, or R5F5631EDDLC#U0 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LQFP), confirmed peripheral set excluding Ethernet MAC, and two validated alternative MCUs with documented functional and packaging differences.
Technical Context
The R5F5631EDDLC#U0 implements the RXv1 CPU core with 5-stage CISC Harvard pipeline, supporting 165 DMIPS at 100 MHz and ultra-compact variable-length instructions. It integrates MPU, JTAG/FINE debug interfaces, and four low-power modes including deep software standby with RTC backup.
Its peripheral suite includes three CAN modules (ISO11898-1 compliant, 32 mailboxes each), up to 13 SCI channels with flexible serial modes (asynchronous, SPI/I²C emulation, LIN), four I²C interfaces (one FM+), three RSPI channels, and hardware CRC/AES-128/192/256 encryption via DEU - all operating from a single 2.7–3.6 V supply.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard, 100 MHz max, 165 DMIPS - enables hard real-time task scheduling with sub-microsecond interrupt latency. |
| Memory | 2 MB flash (no wait states @100 MHz), 128 KB SRAM, 32 KB reprogrammable data flash (100k cycles) - supports field firmware updates without external storage. |
| Analog Peripherals | 21-channel 12-bit A/D (1 µs conversion @50 MHz PCLK), 8-channel 10-bit A/D, 2-channel 10-bit D/A, on-die temperature sensor (±1°C) - suitable for closed-loop motor control and sensor fusion. |
| Communication | 3× CAN (ISO11898-1), 13× SCI (with LIN/Smart Card/I²C/SPI modes), 4× I²C (1 Mbps), 3× RSPI, USB 2.0 full-speed host/function - eliminates need for external protocol bridges in multi-bus industrial nodes. |
| Security & Safety | AES-128/192/256 (ECB/CBC), CRC calculator (X⁸/X¹⁶ polynomials), oscillation-stop detection, IWDT, A/D self-diagnostic - meets IEC60730 Class B requirements out-of-box. |
| Package & Temp | PLQP0176KB-A (176-pin LQFP, 24 × 24 mm, 0.5 mm pitch), -40 to +85°C operating range - compatible with standard SMT assembly and industrial thermal cycling. |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 × 24 mm body, 0.5 mm pitch, exposed pad (thermal enhancement), RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated analog/digital power pins per functional block - enables independent noise filtering and reduces coupling between ADC and digital logic. |
| XTAL / EXTAL | Main clock oscillator input/output | Supports 4–16 MHz crystal - provides high-accuracy timing source for real-time control loops and communication baud rate generation. |
| RESET | Active-low reset input | Accepts asynchronous de-bounced signal - ensures reliable initialization after brown-out or watchdog timeout. |
| IRQ0–IRQ15 | External interrupt inputs | 16 dedicated edge-triggered pins - allows direct connection to safety-critical sensors or emergency stop circuits without GPIO polling. |
| AD000–AD020 | Analog input channels | 21 dedicated 12-bit ADC inputs with sample-and-hold - supports simultaneous sampling across multiple motor phase currents or voltage rails. |
| DA0 / DA1 | Analog output channels | 2× 10-bit voltage-output DACs - drives analog actuators or reference voltages without external DAC ICs. |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730-ready peripherals | Oscillation-stop detection, hardware CRC, IWDT, A/D self-test, and register write protection - reduce certification effort for Class B safety applications. |
| Flexible serial connectivity | SCI modules configurable as UART, SPI, I²C, LIN, or smart-card interface - consolidates multiple external transceivers into one MCU resource. |
| Dual-clock domain operation | Independent ICLK (up to 100 MHz), PCLK (up to 50 MHz), FCLK (up to 50 MHz), BCLK (up to 50 MHz) - enables optimal power/performance trade-off per subsystem. |
| Low-power modes | Sleep, module-stop, software standby, and deep software standby with RTC battery backup - extends runtime in battery-powered HMI or remote I/O nodes. |
| Hardware encryption engine | Dedicated DEU supporting AES-128/192/256 in ECB/CBC modes - accelerates secure boot, firmware authentication, and encrypted data logging. |
Applications
| Industrial PLC I/O Module | Building Automation Controller |
|---|---|
Use Scenario: Central controller managing 32 digital inputs, 16 analog inputs (4–20 mA), and 8 relay outputs in HVAC subsystems. IC Role / Device Role / Timing Role: Main system MCU executing control algorithms, handling Modbus RTU over RS485 (via SCI), and performing real-time PID loop updates every 10 ms. Use Value: Integrated 21-channel 12-bit ADC and 3× CAN eliminate external signal conditioning ICs; 2 MB flash stores multiple firmware versions for fail-safe rollback. |
Use Scenario: Standalone lighting and shade controller interfacing with DALI, KNX, and BACnet MS/TP networks. IC Role / Device Role / Timing Role: Protocol gateway MCU translating between DALI (SCI-based) and KNX (TP-UART via SCI) while maintaining local occupancy-sensing logic. Use Value: 13 SCI channels allow concurrent multi-protocol operation; hardware CRC and AES ensure secure firmware updates over building management network. |
| Motor Drive Feedback Unit | Medical Infusion Pump Controller |
Use Scenario: Compact board measuring motor phase currents, DC bus voltage, and temperature, then communicating fault status via CANopen. IC Role / Device Role / Timing Role: Real-time analog acquisition node synchronizing ADC sampling to PWM carrier edges using MTU2 trigger outputs. Use Value: 1 µs ADC conversion time and deterministic TPU/MTU2 timer triggering enable precise current reconstruction; 128 KB SRAM buffers waveform data for diagnostics. |
Use Scenario: UL/IEC60601-certified infusion pump controlling stepper motor, pressure sensor, and occlusion detection circuitry. IC Role / Device Role / Timing Role: Safety-critical controller running dual-core lockstep verification (via software-implemented redundancy) and monitoring analog sensor health. Use Value: Built-in IEC60730 features (oscillation detection, A/D self-test, IWDT) reduce external safety monitor IC count; 32 KB data flash stores calibration coefficients with 100k-cycle endurance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDLC#U0 | RX63N Group variant with identical package (PLQP0176KB-A), same 2 MB flash/128 KB SRAM, but adds Ethernet MAC (10/100 Mbps MII/RMII) and removes sub-clock oscillator. | Required where wired IP connectivity (e.g., EtherNet/IP, Modbus TCP) is mandatory; unsuitable for cost-sensitive designs where Ethernet adds unnecessary BOM cost. | Select R5F563NEDDLC#U0 only if Ethernet PHY integration is required; otherwise R5F5631EDDLC#U0 offers lower system cost and reduced EMI footprint. |
| R5F566TEBDFP#U0 | RX66T Group MCU in 100-pin LQFP (PLQP0100KB-A), 1.5 MB flash, 256 KB SRAM, no Ethernet, but adds hardware floating-point accelerator and enhanced PWM timers (GPT) optimized for servo control. | Better suited for high-performance motor control (e.g., PMSM FOC) due to GPT's 32-bit resolution and dead-time insertion; lacks 176-pin I/O count for dense I/O applications. | Choose R5F566TEBDFP#U0 when advanced motor control precision outweighs I/O pin count; retain R5F5631EDDLC#U0 for general-purpose industrial control with high peripheral integration. |
Compared with R5F563NEDDLC#U0, the R5F5631EDDLC#U0 saves board space and cost by omitting Ethernet PHY support while retaining identical analog and serial peripheral density; versus R5F566TEBDFP#U0, it trades higher PWM resolution for broader I/O availability and proven qualification in legacy industrial platforms.
Availability
R5F5631EDDLC#U0 is available at Aetrix Electronics and suitable for industrial PLCs, building automation controllers, motor feedback units, and medical infusion pumps requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F5631EDDLC#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX631 Group targets cost-optimized industrial control applications, delivering high integration of analog peripherals, safety features, and multi-protocol connectivity without Ethernet - balancing performance, reliability, and bill-of-materials efficiency.
FAQ
What is the maximum operating frequency and core architecture of the R5F5631EDDLC#U0?
The R5F5631EDDLC#U0 operates at a maximum frequency of 100 MHz using the 32-bit RXv1 CPU core with a 5-stage CISC Harvard pipeline. It delivers 165 DMIPS performance and supports IEEE-754 single-precision floating-point operations - enabling deterministic execution of real-time control algorithms without external co-processors.
Does the R5F5631EDDLC#U0 include an Ethernet MAC controller?
No, the R5F5631EDDLC#U0 belongs to the RX631 Group and explicitly excludes the Ethernet MAC controller. This distinguishes it from the RX63N Group (e.g., R5F563NEDDLC#U0), which integrates a 10/100 Mbps Ethernet MAC with MII/RMII support. The R5F5631EDDLC#U0 relies on external PHY or alternative interfaces like CAN or RS485 for network connectivity.
What package type and pin count does the R5F5631EDDLC#U0 use?
The R5F5631EDDLC#U0 is packaged in PLQP0176KB-A: a 176-pin LQFP with 24 × 24 mm body size and 0.5 mm pitch. This package provides 133 general-purpose I/O pins (18 of which are 5-V tolerant), supporting high-density industrial I/O expansion without requiring BGA assembly infrastructure.
How much on-chip memory does the R5F5631EDDLC#U0 integrate?
The R5F5631EDDLC#U0 integrates 2 MB of on-chip flash memory (executed at 100 MHz with zero wait states), 128 KB of SRAM (also zero-wait), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles - sufficient for storing application code, real-time variables, and field-upgradable calibration data in standalone industrial devices.
Which safety standards does the R5F5631EDDLC#U0 support out-of-the-box?
The R5F5631EDDLC#U0 includes hardware features aligned with IEC60730 Class B requirements: oscillation-stop detection, hardware CRC calculator (X⁸/X¹⁶ polynomials), independent watchdog timer (IWDT), A/D converter self-diagnostic function, and register write protection. These reduce software certification burden for household and industrial appliances.
R5F5631EDDLC#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631EDDLC#U0 FAQ
1.How can I place an order for R5F5631EDDLC#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631EDDLC#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631EDDLC#U0 reliable?
The price and inventory of R5F5631EDDLC#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631EDDLC#U0 is usually 5 days.
3.What payment methods are accepted for R5F5631EDDLC#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631EDDLC#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631EDDLC#U0?
R5F5631EDDLC#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631EDDLC#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631EDDLC#U0?
For technical support, including R5F5631EDDLC#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631EDDLC#U0 requirements.
6.How does Aetrix verify that R5F5631EDDLC#U0 is sourced from the original manufacturer or authorized distributors?
All R5F5631EDDLC#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631EDDLC#U0 meets industry standards.
7.What is the process for return or replacement of R5F5631EDDLC#U0?
All R5F5631EDDLC#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631EDDLC#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631EDDLC#U0 part is unused and in its original packaging.
Return procedure for R5F5631EDDLC#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5631EDDLC#U0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

