Renesas R5F5631JDGFB#V0

Overview

R5F5631JDGFB#V0 from Renesas is a 100 MHz 32-bit RX631 Group microcontroller with integrated FPU, 165 DMIPS performance, 1.5 MB on-chip flash memory, 192 KB SRAM, and 32 KB data flash. It features dual 10-bit D/A converters, 21-channel 12-bit A/D converter with sample-and-hold, Ethernet MAC (excluded in RX631), USB 2.0 host/function interface, CAN, multiple SCI/RSPI/I²C interfaces, and operates from 2.7–3.6 V at –40 to +85°C in a 144-pin LQFP package. It targets industrial control and networked embedded systems requiring deterministic real-time response and peripheral integration.

For engineers reviewing the R5F5631JDGFB#V0 datasheet, R5F5631JDGFB#V0 pinout, R5F5631JDGFB#V0 application, or R5F5631JDGFB#V0 equivalent, this page delivers verified technical context, exact package mapping (PLQP0144KA-A), confirmed peripheral channel counts per package, functional distinctions versus RX63N, and validated alternative MCUs for migration or sourcing continuity.

Technical Context

The R5F5631JDGFB#V0 implements the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code and 165 DMIPS at 100 MHz. It integrates single-precision IEEE-754 FPU, dual multiply-accumulate units, 32-bit multiplier (1-cycle), and 32-bit divider (2-cycle), supporting deterministic real-time computation.

Its peripheral set excludes Ethernet MAC and EDMAC (RX63N-only), but retains full USB 2.0 host/function/OTG support, three CAN channels (ISO 11898-1), up to 13 SCI channels (including LIN-capable SCId), four I²C interfaces (one FM+), three RSPI, and hardware CRC calculator. Clock management includes PLL, HOCO/LOCO oscillators, and independent IWDT clock source.

Key Specifications

Pinout & Package

Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch, exposed thermal pad (non-electrical), RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with R5F563NEDDFB, R5F5631JDGFB#V0 removes Ethernet hardware to lower cost and power, while retaining identical USB, CAN, and analog capabilities. Against R5F566TEBDFB, it trades higher CPU speed and motor-control timers for USB host support and broader communications flexibility-making it optimal for protocol-concentrator and HMI edge nodes.

Availability

R5F5631JDGFB#V0 is available at Aetrix Electronics and suitable for industrial automation controllers, smart energy gateways, factory HMI terminals, and medical diagnostic interfaces requiring stable component supply, long-term lifecycle assurance, and Renesas-qualified production lots.

Supply support for R5F5631JDGFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.

The RX631 Group is designed for cost-sensitive, high-integration industrial and consumer applications requiring rich peripheral sets-including USB, CAN, and precision analog-without Ethernet, balancing performance, footprint, and bill-of-materials efficiency.

FAQ

What is the maximum operating frequency and core architecture of the R5F5631JDGFB#V0?

The R5F5631JDGFB#V0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instruction set. It delivers 165 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, 32-bit hardware multiplier (1-cycle), and 32-bit divider (2-cycle). This architecture enables deterministic real-time execution and compact code density critical for embedded control applications.

Does the R5F5631JDGFB#V0 include an Ethernet MAC controller?

No, the R5F5631JDGFB#V0 does not include an Ethernet MAC controller. It belongs to the RX631 Group, which explicitly excludes Ethernet functionality present in the RX63N Group. The R5F5631JDGFB#V0 retains full USB 2.0 host/function/OTG, CAN, SCI, I²C, and RSPI interfaces-but requires an external Ethernet PHY and MAC controller (e.g., LAN8720A with SPI or parallel interface) if network connectivity is needed.

What are the memory resources available on the R5F5631JDGFB#V0?

The R5F5631JDGFB#V0 integrates 1.5 MB of on-chip flash memory (executed at 100 MHz with zero wait states), 192 KB of SRAM (also zero-wait), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. Flash supports on-board programming via SWD/JTAG or off-board parallel programming (enabled for ≥100-pin packages). SRAM includes backup capability in deep software standby mode using VBATT.

Which package type and pin count does the R5F5631JDGFB#V0 use?

The R5F5631JDGFB#V0 uses the PLQP0144KA-A package: a 144-pin LQFP with 20 × 20 mm body size, 0.5 mm pin pitch, and exposed thermal pad. This package supports 111 general-purpose I/O pins (including 18 with 5-V tolerance), pull-up resistors on all I/O, open-drain outputs, and dedicated pins for USB, CAN, SCI, and external clock sources-matching Renesas' standard RX631 footprint for drop-in compatibility across the group.

How does the R5F5631JDGFB#V0 support functional safety standards like IEC60730?

The R5F5631JDGFB#V0 includes hardware features required for Class B IEC60730 compliance: oscillation-stop detection for main/sub clocks, dedicated IWDT with independent LOCO clock, CRC calculator (with three selectable polynomials), self-diagnostic function for the 10-bit A/D converter, and memory protection unit (MPU) for runtime code/data isolation. These are documented in Renesas Application Note R01AN1379 and enabled via configuration registers-not software-only checks.