Renesas R5F5631KDDFP#V0
- Part No.:
- R5F5631KDDFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F5631KDDFP#V0.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,717
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5631KDDFP#V0 from Renesas is a 100 MHz 32-bit RX CPU-based microcontroller in the RX631 Group, featuring 2 MB on-chip flash memory, 192 KB SRAM, 32 KB data flash, and integrated 12-bit/10-bit A/D converters, 10-bit D/A converters, RTC, and USB 2.0 function controller - designed for industrial HMI, motor control, and networked embedded systems without Ethernet.
For engineers reviewing the R5F5631KDDFP#V0 datasheet, R5F5631KDDFP#V0 pinout, R5F5631KDDFP#V0 application, or R5F5631KDDFP#V0 equivalent, this part supports full-speed USB 2.0 device operation, CAN 2.0B (2 channels), up to 13 SCI interfaces, I²C (4 channels), RSPI (3 channels), and operates across -40°C to +85°C with 2.7–3.6 V supply.
Technical Context
The R5F5631KDDFP#V0 implements the RXv1 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU delivering 165 DMIPS at 100 MHz. It integrates a memory protection unit (MPU), JTAG/FINE debug interfaces, and supports little-endian or big-endian data arrangement.
Its peripheral set excludes Ethernet MAC and sub-clock oscillator (unlike RX63N), but includes dual CAN modules (32 mailboxes total), programmable pulse generator (PPG), MTU2/TPU timers, and parallel data capture unit (PDC) - all synchronized to independent clock domains (ICLK up to 100 MHz, PCLK up to 50 MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC core with 5-stage pipeline, 165 DMIPS @ 100 MHz, IEEE-754 FPU, MPU support |
| Flash Memory | 2 Mbytes main flash, zero-wait-state access at 100 MHz, on-board/off-board programmable |
| RAM & Data Flash | 192 Kbytes SRAM (no-wait), 32 Kbytes reprogrammable data flash (100,000 erase/write cycles) |
| Analog Peripherals | 21-channel 12-bit A/D (1 µs conversion), 8-channel 10-bit A/D, 2-channel 10-bit D/A, on-die temperature sensor (±1°C) |
| Communication Interfaces | USB 2.0 full-speed function controller (2 KB buffer), CAN ×2 (ISO 11898-1, 32 mailboxes), SCI ×13, I²C ×4 (1 Mbps), RSPI ×3 |
| Timers & Control | MTU2 (6 ch), TPU (12 ch), TMR (4 ch), CMT (4 ch), RTC with battery backup, IWDT with dedicated LOCO clock |
| Package & Environment | LQFP-100 (PLQP0100KB-A), 14 × 14 mm, 0.5 mm pitch, -40°C to +85°C operating range (D version) |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 × 14 mm body, 0.5 mm pitch, exposed pad (thermal pad not electrically connected). Pin count and I/O configuration match RX631 Group specification for 100-pin packages: 78 general-purpose I/O pins, 1 input-only pin, 17 pins 5-V tolerant, all with pull-up and open-drain capability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated analog/digital power rails; AVCC0 = VREFH = VCC_USB = 2.7–3.6 V; separate VBATT pin for RTC backup |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; PLL generates system clock up to 100 MHz |
| MD0 / MD1 | Mode selection inputs | Configure boot mode (single-chip, ROM-enabled/disabled expansion) at reset; pulled internally during startup |
| RESET | Active-low reset input | Asynchronous reset assertion; internal POR/LVD ensures reliable initialization under varying supply conditions |
| USB_VBUS / USB_ID | USB detection signals | VBUS monitors host power presence; ID selects OTG role (function-only mode active for R5F5631KDDFP#V0) |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | Full-duplex UART interface with baud-rate generator; supports LIN protocol via SCId channel |
| TXD1 / RXD1 | SCI1 asynchronous serial interface | Independent UART with software-selectable LSB/MSB-first transfer and average-rate clock input from TMR |
| SDA0 / SCL0 | I²C bus interface channel 0 | FM+ compliant (1 Mbps), multi-master capable, supports SMBus protocols and clock stretching |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware accelerator enables deterministic real-time math for motor control and sensor fusion |
| Low-power operation | 500 µA/MHz active current; four low-power modes (sleep, module-stop, software standby, deep software standby) with RTC retention |
| Secure boot & diagnostics | IEC 60730-compliant features: oscillation-stop detection, CRC calculator (3 polynomials), self-diagnostic A/D, IWDT |
| Flexible timer subsystem | MTU2 + TPU + PPG enable complex waveform generation (complementary PWM, phase counting, encoder input) with trigger chaining to A/D |
| Robust communication stack | Dual CAN controllers with 32 mailboxes each, USB 2.0 function controller with 2 KB RAM buffer, and 13 SCI channels with LIN support |
Applications
| Industrial HMI Panel | Smart Motor Drive Controller |
|---|---|
Use Scenario: Standalone touch-based operator interface with local logic, display refresh, and fieldbus connectivity. IC Role / Device Role / Timing Role: Main application MCU handling GUI rendering, button scanning, CAN/SCI communication, and real-time status updates. Use Value: Integrated 2 MB flash stores firmware + graphics assets; 192 KB SRAM buffers display frame data; USB function enables field firmware updates. |
Use Scenario: Closed-loop BLDC/PMSM drive with position sensing, current feedback, and safety monitoring. IC Role / Device Role / Timing Role: Real-time motion controller executing FOC algorithms using FPU, generating PWM via MTU2/TPU, and sampling ADC at 1 µs resolution. Use Value: Deterministic 100 MHz timing, 12-bit ADC with sample-and-hold, and complementary PWM output mode ensure precise torque control. |
| Networked Building Sensor Node | Programmable Logic Relay |
Use Scenario: Multi-sensor environmental node (temp, humidity, CO₂) with wired CAN/RS485 and USB configuration port. IC Role / Device Role / Timing Role: Sensor aggregator and protocol translator interfacing analog sensors, digital I/O, and field buses. Use Value: On-die ±1°C temperature sensor reduces BOM cost; 10-bit D/A drives analog outputs; CAN + SCI provide dual-fieldbus redundancy. |
Use Scenario: DIN-rail mounted relay module with configurable I/O mapping, time-based sequencing, and remote diagnostics. IC Role / Device Role / Timing Role: Programmable logic engine implementing ladder logic or state machines with deterministic scan cycle timing. Use Value: 4 low-power modes extend uptime during idle; RTC with alarm interrupt enables scheduled operations; 78 GPIOs support flexible I/O assignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NDDFP#V0 | RX63N variant: adds Ethernet MAC, RMII/MII, EDMAC, sub-clock oscillator, and battery backup RTC - same 2 MB flash, 192 KB SRAM, LQFP-100 package | Required for Ethernet-connected gateways or IoT edge nodes needing TCP/IP offload | Select R5F563NDDFP#V0 only if Ethernet PHY interface and associated DMA resources are needed; otherwise R5F5631KDDFP#V0 reduces BOM and layout complexity |
| R5F566TEADFP#V0 | RX66T Group part: 160 MHz CPU, FPU, 2 MB flash, 384 KB SRAM, enhanced MTU3 timers, no USB function controller, added encoder interface | Targeted at high-performance servo drives requiring >100 kHz PWM update rates and dual encoder inputs | R5F566TEADFP#V0 suits demanding motion control where CPU throughput and timer precision exceed RX631 capabilities; lacks USB, so requires external bridge for firmware updates |
Compared with R5F563NDDFP#V0, the R5F5631KDDFP#V0 removes Ethernet and sub-clock circuitry to reduce cost and power, while retaining identical USB, CAN, and analog peripherals; versus R5F566TEADFP#V0, it trades higher clock speed and advanced timers for lower cost, USB integration, and broader peripheral compatibility in mid-tier industrial control.
Availability
R5F5631KDDFP#V0 is available at Aetrix Electronics and suitable for industrial HMI, smart motor drives, building automation sensor nodes, and programmable logic relays requiring stable component supply, long-lifecycle support, and qualified automotive/industrial-grade sourcing.
Supply support for R5F5631KDDFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group - including R5F5631KDDFP#V0 - was engineered for cost-sensitive, real-time industrial control applications requiring rich analog integration, deterministic USB/CAN connectivity, and functional safety readiness without Ethernet overhead.
FAQ
What is the maximum operating frequency and CPU performance of the R5F5631KDDFP#V0?
The R5F5631KDDFP#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using its 32-bit RXv1 CPU core with integrated IEEE-754 single-precision floating-point unit. Its 5-stage pipeline, variable-length instruction set, and hardware multiplier/divider enable deterministic real-time execution critical for motor control and sensor processing tasks within the R5F5631KDDFP#V0's architecture.
Does the R5F5631KDDFP#V0 include Ethernet capability?
No, the R5F5631KDDFP#V0 belongs to the RX631 Group, which explicitly excludes the Ethernet MAC, EDMAC, and RMII/MII interfaces present in the RX63N Group. This omission reduces silicon area, power consumption, and system-level design complexity - making the R5F5631KDDFP#V0 ideal for applications requiring USB, CAN, and SCI connectivity without Ethernet PHY integration or associated PCB routing constraints.
What are the memory resources available on the R5F5631KDDFP#V0?
The R5F5631KDDFP#V0 integrates 2 Mbytes of on-chip flash memory (zero-wait-state at 100 MHz), 192 Kbytes of SRAM (also zero-wait), and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles. These resources support complex firmware, real-time data buffering, and non-volatile parameter storage - all accessible without external memory controllers, simplifying design for space-constrained industrial applications using the R5F5631KDDFP#V0.
Which communication interfaces does the R5F5631KDDFP#V0 support?
The R5F5631KDDFP#V0 supports USB 2.0 full-speed function controller (with 2 KB buffer), two CAN 2.0B modules (32 mailboxes total), up to 13 SCI channels (including LIN-capable SCId), four I²C interfaces (one FM+, up to 1 Mbps), and three RSPI channels. It does not include Ethernet, OTG host capability, or IEBus - distinguishing it from RX63N and confirming its positioning for USB/CAN-centric embedded control using the R5F5631KDDFP#V0.
What is the package type and thermal specification for the R5F5631KDDFP#V0?
The R5F5631KDDFP#V0 uses the PLQP0100KB-A package: a 100-pin LQFP with 14 × 14 mm body size, 0.5 mm pitch, and exposed thermal pad. It is rated for industrial temperature range (-40°C to +85°C) as a D-version device, with supply voltage requirements of 2.7–3.6 V on VCC/AVCC0/VREFH/VCC_USB and 2.0–3.6 V on VBATT - ensuring robust operation in harsh environments typical of applications deploying the R5F5631KDDFP#V0.
R5F5631KDDFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 14x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631KDDFP#V0 FAQ
1.How can I place an order for R5F5631KDDFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631KDDFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631KDDFP#V0 reliable?
The price and inventory of R5F5631KDDFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631KDDFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F5631KDDFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631KDDFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631KDDFP#V0?
R5F5631KDDFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631KDDFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631KDDFP#V0?
For technical support, including R5F5631KDDFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631KDDFP#V0 requirements.
6.How does Aetrix verify that R5F5631KDDFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F5631KDDFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631KDDFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F5631KDDFP#V0?
All R5F5631KDDFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631KDDFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631KDDFP#V0 part is unused and in its original packaging.
Return procedure for R5F5631KDDFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5631KDDFP#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

