Renesas R5F5631KDGFB#V0
- Part No.:
- R5F5631KDGFB#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5631KDGFB#V0.pdf
- Description:
- 32BIT MCU RX631
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631KDGFB#V0 from Renesas is a 100 MHz, 32-bit RX CPU core microcontroller in the RX631 Group, featuring 2 MB on-chip flash memory, 192 KB SRAM, 32 KB data flash, and integrated 12-bit/10-bit A/D converters, 10-bit D/A converters, RTC, and USB 2.0 function controller - but no Ethernet MAC or SDRAM interface. It targets industrial HMI, motor control, and networked sensor nodes where cost-optimized connectivity and deterministic real-time performance are required.
For engineers reviewing the R5F5631KDGFB#V0 datasheet, R5F5631KDGFB#V0 pinout, R5F5631KDGFB#V0 application, or R5F5631KDGFB#V0 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-A (144-pin LQFP), confirmed peripheral channel counts per package, functional distinctions from RX63N variants, and two validated alternative parts for design flexibility.
Technical Context
The R5F5631KDGFB#V0 implements the RXv1 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU delivering 165 DMIPS at 100 MHz. It supports little-endian or big-endian data arrangement and includes MPU for memory protection.
Its clock system integrates PLL, 125-kHz LOCO, and 50-MHz HOCO oscillators with independent division/multiplication for ICLK (up to 100 MHz), PCLK (up to 50 MHz), FCLK (up to 50 MHz), and BCLK (up to 50 MHz). The device operates from a single 2.7–3.6 V supply and supports four low-power modes including deep software standby with RTC backup.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC core with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK), enabling deterministic real-time execution |
| Flash Memory | 2 MB on-chip main flash, zero-wait-state access at 100 MHz |
| SRAM | 192 KB on-chip SRAM, zero-wait-state access for instruction and operand storage |
| A/D Converter | 21-channel 12-bit + 8-channel 10-bit SAR ADC with sample-and-hold and trigger-based conversion start |
| D/A Converter | 2-channel 10-bit voltage-output DAC with 0 V to VREFH range |
| USB Interface | Full-speed USB 2.0 function controller only (no host/OTG), 2 KB on-chip buffer |
| Operating Temperature | –40°C to +85°C (D version), suitable for industrial ambient conditions |
Pinout & Package
Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm, 0.5 mm pitch, RoHS-compliant, surface-mount.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | 14 dedicated VCC and 14 VSS pins distributed across perimeter for stable core/peripheral rail decoupling |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal for precise system timing and PLL reference |
| RESET | Active-low reset input | Asynchronous reset assertion compatible with external POR circuits and JTAG debugging |
| MD0 / MD1 | Mode selection inputs | Configure boot mode (ROM/flash) and debug interface (JTAG/FINE) at power-on |
| USB_DP / USB_DM | USB differential data lines | Full-speed (12 Mbps) USB 2.0 physical layer interface, internal transceiver, no external PHY required |
| AD000–AD020 | Analog input channels | 21 dedicated pins for 12-bit ADC; AD000–AD007 also support 10-bit ADC alternate function |
| DA0 / DA1 | Digital-to-analog outputs | Two buffered voltage-output DAC channels referenced to VREFH (2.7–3.6 V) |
| RTC_VDD / RTC_VSS | RTC backup power domain | Separate 2.0–3.6 V battery-supply pins enabling calendar/clock operation during main power loss |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware accelerator enables real-time math for motor control and sensor fusion without software emulation overhead |
| Data encryption unit (DEU) | AES-128/192/256 ECB/CBC acceleration supports secure firmware updates and encrypted communication in industrial IoT endpoints |
| Programmable pulse generator (PPG) | 32-channel pulse output synchronized to MTU2/TPU timers, ideal for multi-phase motor gate drive timing |
| Temperature sensor | On-die ±1°C accuracy sensor digitized via 12-bit ADC, enabling thermal monitoring without external components |
| Register write protection | Hardware-enforced lock bits prevent accidental overwrites of critical registers (e.g., clock dividers, interrupt vectors) in field-deployed systems |
| CRC calculator | Configurable 8-/16-bit CRC engine with three polynomials supports robust data integrity checking for flash updates and CAN/SCI frame validation |
Applications
| Industrial HMI Panel | Motor Control Drive |
|---|---|
|
Use Scenario: Standalone touch-enabled display with local logic for status visualization, parameter adjustment, and alarm logging in factory equipment. IC Role / Device Role / Timing Role: Main application processor executing GUI framework, managing USB HID interface to PC host, and sampling analog feedback signals. Use Value: Integrated 2 MB flash stores full UI assets and firmware; 192 KB SRAM buffers graphics rendering; USB function controller enables plug-and-play configuration without external hub IC. |
Use Scenario: Closed-loop BLDC motor controller with Hall-effect sensing, PWM generation, and current feedback in HVAC blowers or pumps. IC Role / Device Role / Timing Role: Real-time motion controller generating complementary PWM waveforms, capturing encoder edges, and executing FOC algorithms using FPU. Use Value: MTU2 and TPU modules deliver sub-microsecond PWM dead-time control; 12-bit ADC samples phase currents at 1 µs/channel; DEU secures firmware updates over CAN. |
| Smart Sensor Node | Building Automation Controller |
|
Use Scenario: Battery-powered environmental sensor node aggregating temperature, humidity, and CO₂ readings for wireless gateway transmission. IC Role / Device Role / Timing Role: Low-power data acquisition engine with RTC-triggered wake-up, ADC scanning, and USB-based firmware update capability. Use Value: Deep software standby draws <500 µA/MHz; on-chip temperature sensor eliminates external thermistor; 32 KB data flash logs sensor history with 100k-cycle endurance. |
Use Scenario: DIN-rail mounted HVAC controller coordinating fan speed, valve position, and occupancy detection across multiple zones. IC Role / Device Role / Timing Role: Central coordination MCU interfacing with RS-485 (SCI), I²C sensors, and analog actuators while maintaining time-of-day scheduling. Use Value: 13 SCI channels support multi-drop Modbus RTU networks; RTC with battery backup maintains schedule integrity during mains failure; 48 GPIOs manage discrete I/O and LED indicators. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NKHDFB#V0 | RX63N variant with identical 144-pin LQFP package, 2 MB flash, 192 KB SRAM, but adds Ethernet MAC and SDRAM controller | Required for wired IP-connected devices (e.g., IIoT edge gateways); unnecessary if Ethernet is omitted to reduce BOM cost and layout complexity | Select R5F563NKHDFB#V0 only when 10/100 Mbps Ethernet or external SDRAM expansion is mandatory; otherwise R5F5631KDGFB#V0 reduces component count and PCB layer count. |
| R5F562T7DDFK#V0 | RX62T Group part in 100-pin LQFP; 512 KB flash, 64 KB SRAM, no USB, no DEU, but enhanced motor control peripherals (MTU3, encoder interfaces) | Optimized for high-volume, cost-sensitive motor drives where USB and security are not needed and smaller footprint is preferred | Choose R5F562T7DDFK#V0 for pure motor control applications with tight space constraints and no need for USB or AES; retains same toolchain compatibility. |
Compared with R5F563NKHDFB#V0, R5F5631KDGFB#V0 removes Ethernet and SDRAM support to lower system cost and simplify layout, while retaining full USB, FPU, and DEU capabilities. Against R5F562T7DDFK#V0, it offers double the memory, USB connectivity, and cryptographic acceleration - making it better suited for feature-rich HMI or secure sensor aggregation.
Availability
R5F5631KDGFB#V0 is available at Aetrix Electronics and suitable for industrial HMI, motor control, smart sensor nodes, and building automation controllers requiring stable component supply, long-term lifecycle assurance, and full production traceability.
Supply support for R5F5631KDGFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is designed for cost-conscious industrial applications demanding real-time determinism, rich analog integration, and USB connectivity - without the added complexity and cost of Ethernet or external memory interfaces.
FAQ
What is the maximum operating frequency and CPU performance of the R5F5631KDGFB#V0?
The R5F5631KDGFB#V0 operates at a maximum system clock frequency of 100 MHz and delivers 165 DMIPS using its 32-bit RXv1 CPU core with integrated single-precision IEEE-754 FPU. This performance level supports real-time control loops, floating-point sensor fusion, and responsive GUI rendering without external co-processors.
Does the R5F5631KDGFB#V0 include an Ethernet MAC controller?
No, the R5F5631KDGFB#V0 belongs to the RX631 Group, which explicitly excludes the Ethernet MAC and associated EDMAC found in the RX63N Group. This omission reduces pin count, power consumption, and layout complexity for applications where wired IP networking is unnecessary.
What package type and pin count does the R5F5631KDGFB#V0 use?
The R5F5631KDGFB#V0 uses the PLQP0144KA-A package: a 144-pin LQFP measuring 20 × 20 mm with 0.5 mm pitch. This package provides 111 general-purpose I/O pins, 18 of which are 5-V tolerant, and supports full peripheral functionality including USB, CAN, and multiple SCI/I²C interfaces.
How much on-chip memory does the R5F5631KDGFB#V0 integrate?
The R5F5631KDGFB#V0 integrates 2 MB of on-chip flash memory (zero-wait-state at 100 MHz), 192 KB of on-chip SRAM (zero-wait-state), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles - sufficient for dual-bank firmware updates and persistent parameter storage.
Is the R5F5631KDGFB#V0 supported by Renesas' E2 Studio and CS+ development tools?
Yes, the R5F5631KDGFB#V0 is fully supported by Renesas' E2 Studio IDE and CS+ integrated development environment, including debug via JTAG/FINE interfaces, peripheral configuration wizards, and RX compiler toolchain. Renesas-provided HAL libraries and example projects for USB, ADC, and motor control are directly applicable to R5F5631KDGFB#V0.
R5F5631KDGFB#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631KDGFB#V0 FAQ
1.How can I place an order for R5F5631KDGFB#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631KDGFB#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631KDGFB#V0 reliable?
The price and inventory of R5F5631KDGFB#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631KDGFB#V0 is usually 5 days.
3.What payment methods are accepted for R5F5631KDGFB#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631KDGFB#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631KDGFB#V0?
R5F5631KDGFB#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631KDGFB#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631KDGFB#V0?
For technical support, including R5F5631KDGFB#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631KDGFB#V0 requirements.
6.How does Aetrix verify that R5F5631KDGFB#V0 is sourced from the original manufacturer or authorized distributors?
All R5F5631KDGFB#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631KDGFB#V0 meets industry standards.
7.What is the process for return or replacement of R5F5631KDGFB#V0?
All R5F5631KDGFB#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631KDGFB#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631KDGFB#V0 part is unused and in its original packaging.
Return procedure for R5F5631KDGFB#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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