Renesas R5F5631NDGFL#V0
- Part No.:
- R5F5631NDGFL#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
R5F5631NDGFL#V0.pdf
- Description:
- 32BIT MCU RX631 384K LQFP48 -40/
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631NDGFL#V0 from Renesas is a 100 MHz 32-bit RX CPU-based microcontroller in the RX631 Group, featuring 512 KB on-chip flash memory, 64 KB SRAM, 32 KB data flash, and integrated 12-bit/10-bit A/D converters, 10-bit D/A converters, RTC, and CAN interface - designed for industrial control and networked embedded systems without Ethernet.
For engineers reviewing the R5F5631NDGFL#V0 datasheet, R5F5631NDGFL#V0 pinout, R5F5631NDGFL#V0 application, or R5F5631NDGFL#V0 equivalent, key selection criteria include its 176-pin LQFP package, -40 to +85°C operating range, absence of Ethernet MAC (distinguishing it from RX63N), support for up to 13 channels of SCI, 4-channel I²C, 3-channel CAN, and USB 2.0 host/function capability.
Technical Context
The R5F5631NDGFL#V0 implements the RXv1 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions, delivering 165 DMIPS at 100 MHz while supporting IEEE-754 single-precision floating-point operations and dual multiply-accumulate units. It integrates a memory protection unit (MPU) and JTAG/FINE debugging interfaces.
Its peripheral set includes three CAN modules (ISO 11898-1 compliant, 32 mailboxes each), four I²C interfaces (one FM+ capable of 1 Mbps), thirteen serial communication interfaces (SCI) with flexible mode selection (asynchronous, SPI-like, I²C-like, smart-card), and a dedicated DMA controller with four channels - all clocked from a configurable PCLK domain up to 50 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC core with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK); peripheral clock (PCLK) up to 50 MHz |
| Flash Memory | 512 KB main flash, zero-wait-state operation at 100 MHz |
| SRAM | 64 KB on-chip SRAM, zero-wait-state access for both instructions and data |
| A/D Converter | 21-channel 12-bit S12AD + 8-channel 10-bit AD, 1.0 µs conversion time @ 50 MHz PCLK |
| D/A Converter | 2-channel 10-bit DA output, voltage range 0 V to VREFH |
| Package & Pins | 176-pin LQFP (PLQP0176KB-A), 0.5 mm pitch, 24 × 24 mm footprint |
| Operating Temperature | -40°C to +85°C (D version), qualified for industrial environments |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 × 24 mm, 0.5 mm pitch, exposed pad (thermal pad not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Multiple dedicated pairs for analog/digital domains; decoupling required per Renesas layout guidelines |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables high-accuracy system timing and PLL reference |
| MD0 / MD1 | Mode configuration pins | Set boot mode (single-chip, ROM-enabled/disabled expansion) at reset; pulled internally during startup |
| RESET | Active-low reset input | Asynchronous reset assertion; compatible with external POR circuits and watchdog outputs |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 full-speed transceiver interface | Enables host/function/OTG operation; VBUS detection supports bus-powered/self-powered mode switching |
| TXDn / RXDn (SCI) | Asynchronous serial transmit/receive | Up to 13 independent SCI channels; configurable baud rate, parity, stop bits, and framing via on-chip baud generator |
| TXDn / RXDn (CAN) | CAN physical layer interface | Three independent CAN modules; each supports standard/extended frames, 32 mailboxes, and loopback self-test mode |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware accelerator enabling deterministic real-time math for motor control or sensor fusion |
| Memory Protection Unit (MPU) | Configurable region-based access control for flash, RAM, and peripherals - essential for IEC 60730 Class B compliance |
| Data Encryption Unit (DEU) | AES-128/192/256 encryption/decryption in ECB/CBC modes for secure firmware updates and data-at-rest protection |
| Real-time Clock (RTC) | Calendar/clock with alarm, periodic interrupt, and time-capture on external event - operates from subclock (32.768 kHz) with battery backup |
| Low-power modes | Four distinct modes (Sleep, All-module clock stop, Software standby, Deep software standby) with sub-µA retention current |
| On-chip debugging | Full JTAG and two-wire FINE interface support for non-intrusive trace, breakpoint, and register inspection during development |
Applications
| Industrial PLC I/O Module | Smart Energy Metering Gateway |
|---|---|
Use Scenario: Standalone DIN-rail-mounted I/O module collecting analog sensor inputs, driving digital outputs, and communicating over CAN bus to central controller. IC Role / Device Role / Timing Role: Main system controller executing real-time I/O scanning, CAN protocol stack, and local diagnostics. Use Value: Integrated 21-channel 12-bit A/D and 3-channel CAN eliminate external ADCs and transceivers; 512 KB flash accommodates dual-bank firmware for safe field updates. |
Use Scenario: Two-way communication gateway aggregating data from multiple utility meters (via RS-485/SCI) and forwarding via CAN or USB to concentrator or HMI. IC Role / Device Role / Timing Role: Protocol translation hub with time-stamped data logging and secure firmware update handling. Use Value: RTC with battery backup ensures accurate timestamping across power cycles; DEU enables AES-encrypted firmware delivery compliant with DLMS/COSEM security profiles. |
| Factory Automation HMI Controller | Medical Diagnostic Sensor Interface |
Use Scenario: Embedded HMI panel controlling machine sequences, displaying status, and logging events via SD card or USB mass storage. IC Role / Device Role / Timing Role: Application processor managing GUI rendering, peripheral I/O, and USB device/host functions. Use Value: USB 2.0 host/function supports plug-and-play USB peripherals (keyboards, flash drives); 13-channel SCI enables simultaneous connection to multiple legacy industrial devices. |
Use Scenario: Portable diagnostic device acquiring temperature, ECG, and impedance signals, then transmitting processed results via USB or CAN. IC Role / Device Role / Timing Role: Signal acquisition and preprocessing engine with calibrated analog front-end and safety-critical timing. Use Value: On-chip temperature sensor (±1°C accuracy) calibrates A/D references; MPU and IWDT support IEC 62304 Class C software safety requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDFC | RX63N variant with identical 176-pin LQFP package, 2 MB flash, 256 KB SRAM, and added Ethernet MAC + RMII/MII interface | Required where IEEE 802.3 connectivity (e.g., industrial Ethernet I/O) is mandatory; higher BOM cost and larger code footprint | Select only if Ethernet PHY integration is needed; otherwise R5F5631NDGFL#V0 offers better cost/performance for CAN/USB-only systems |
| R5F566TEBDFP | RX66T Group MCU, 176-pin LQFP, 160 MHz, 1 MB flash, 256 KB SRAM, enhanced PWM timers (MTU3), no Ethernet or USB host | Targeted at high-performance motor control (3-phase inverters, servo drives); lacks USB/IEBus but adds encoder interfaces and faster ADC | Prefer for real-time motor control with >100 kHz PWM; R5F5631NDGFL#V0 remains optimal for mixed-protocol industrial gateways |
Compared with R5F563NEDDFC, R5F5631NDGFL#V0 reduces system complexity by omitting Ethernet PHY support while retaining full CAN/USB/SCI functionality; versus R5F566TEBDFP, it trades higher PWM resolution for broader communications flexibility and lower cost in non-motor-control roles.
Availability
R5F5631NDGFL#V0 is available at Aetrix Electronics and suitable for industrial automation, smart metering, and factory HMI applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for R5F5631NDGFL#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is engineered for cost-sensitive industrial control applications demanding rich peripheral integration, functional safety readiness (IEC 60730), and deterministic real-time performance - without the overhead of Ethernet hardware.
FAQ
What is the maximum operating frequency and core type of the R5F5631NDGFL#V0?
The R5F5631NDGFL#V0 features a 32-bit RXv1 CPU core with a maximum operating frequency of 100 MHz, delivering 165 DMIPS performance. Its Harvard architecture with 5-stage pipeline and variable-length instruction set enables ultra-compact code density and deterministic execution timing critical for industrial real-time tasks.
Does the R5F5631NDGFL#V0 include an Ethernet MAC controller?
No, the R5F5631NDGFL#V0 belongs to the RX631 Group and does not integrate an Ethernet MAC controller. That feature is exclusive to the RX63N Group (e.g., R5F563NEDDFC). The R5F5631NDGFL#V0 instead emphasizes CAN, USB 2.0 host/function, and multiple SCI interfaces for industrial fieldbus connectivity.
What are the memory resources available on the R5F5631NDGFL#V0?
The R5F5631NDGFL#V0 includes 512 KB of on-chip flash memory (zero-wait-state at 100 MHz), 64 KB of SRAM (zero-wait-state), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These resources support robust firmware partitioning, data logging, and field-upgrade capabilities without external memory.
Which communication interfaces are supported by the R5F5631NDGFL#V0?
The R5F5631NDGFL#V0 supports three CAN 2.0B modules (32 mailboxes each), four I²C interfaces (including one FM+ at 1 Mbps), thirteen SCI channels (with asynchronous, SPI-like, and smart-card modes), three RSPI channels, one USB 2.0 full-speed host/function/OTG module, and optional IEBus - making it ideal for multi-protocol industrial gateways.
Is the R5F5631NDGFL#V0 qualified for industrial temperature range operation?
Yes, the R5F5631NDGFL#V0 is a D-version device rated for -40°C to +85°C operation, fully qualified for industrial environments. It includes low-voltage detection (LVD), independent watchdog timer (IWDT), and built-in oscillation-stop detection - all supporting IEC 60730 Class B compliance for safety-critical embedded control.
R5F5631NDGFL#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 30
- Program Memory Size:
- 384KB (384K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631NDGFL#V0 FAQ
1.How can I place an order for R5F5631NDGFL#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631NDGFL#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631NDGFL#V0 reliable?
The price and inventory of R5F5631NDGFL#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631NDGFL#V0 is usually 5 days.
3.What payment methods are accepted for R5F5631NDGFL#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631NDGFL#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631NDGFL#V0?
R5F5631NDGFL#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631NDGFL#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631NDGFL#V0?
For technical support, including R5F5631NDGFL#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631NDGFL#V0 requirements.
6.How does Aetrix verify that R5F5631NDGFL#V0 is sourced from the original manufacturer or authorized distributors?
All R5F5631NDGFL#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631NDGFL#V0 meets industry standards.
7.What is the process for return or replacement of R5F5631NDGFL#V0?
All R5F5631NDGFL#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631NDGFL#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631NDGFL#V0 part is unused and in its original packaging.
Return procedure for R5F5631NDGFL#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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