Renesas R5F5631WDDFP#V0
- Part No.:
- R5F5631WDDFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F5631WDDFP#V0.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5631WDDFP#V0 from Renesas is a 100 MHz 32-bit RX CPU-based microcontroller in the RX631 Group, featuring 1 MB on-chip flash memory, 128 KB SRAM, 32 KB data flash, and integrated 12-bit/10-bit A/D converters, 10-bit D/A converters, RTC, USB 2.0 function controller, CAN, I²C, SPI, and SCI interfaces - designed for industrial control and networked embedded systems requiring deterministic real-time performance.
For engineers reviewing the R5F5631WDDFP#V0 datasheet, R5F5631WDDFP#V0 pinout, R5F5631WDDFP#V0 application, or R5F5631WDDFP#V0 equivalent, this MCU delivers verified 100 MHz operation, IEEE-754 FPU support, 5-V-tolerant I/Os, low-power modes (down to 500 µA/MHz), and IEC60730-compliant safety features including CRC, self-diagnostic A/D, and oscillation-stop detection.
Technical Context
The R5F5631WDDFP#V0 implements the CISC Harvard-architecture RX CPU core with 5-stage pipeline, variable-length instructions, and MPU support - enabling ultra-compact code and fast interrupt response. It operates from a single 2.7–3.6 V supply and integrates dedicated clock domains (ICLK up to 100 MHz, PCLK up to 50 MHz) for system, peripheral, FlashIF, and external bus timing.
It belongs to the RX631 Group (non-Ethernet variant), distinguishing it from the RX63N Group by omission of Ethernet MAC and EDMAC. Its peripheral set includes three CAN channels (32 mailboxes each), up to 13 SCI channels (with LIN/Smart Card/I²C/SPI emulation), four I²C interfaces (one FM+), three RSPI modules, and parallel data capture unit (PDC) support for image sensor interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK), enabling real-time deterministic execution |
| Flash Memory | 1 MB on-chip main flash, zero-wait-state access at 100 MHz |
| SRAM | 128 KB on-chip SRAM, no-wait access for instruction and operand storage |
| Data Flash | 32 KB reprogrammable E² data flash, rated for 100,000 erase/write cycles |
| A/D Converter | 21-channel 12-bit + 8-channel 10-bit simultaneous-sampling A/D with sample-and-hold |
| D/A Converter | 2-channel 10-bit voltage-output DAC (0 V to VREFH) |
| Operating Temperature | −40 °C to +85 °C (D version), validated for industrial ambient conditions |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 × 14 mm body, 0.5-mm pitch, exposed pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Core I/O supply pins (2.7–3.6 V); multiple VCC/VSS pairs ensure stable decoupling and noise immunity |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal for precise system clock generation |
| RESET | Active-low reset input | Asynchronous hardware reset with internal pull-up; compatible with external reset supervisors |
| IRQ0–IRQ15 | External interrupt inputs | 16 dedicated edge-triggered interrupt pins with configurable polarity and priority |
| USB_VBUS / USB_D+/D− | USB 2.0 full-speed interface | Integrated transceiver supports bus-powered or self-powered USB device mode (12 Mbps) |
| TXD0/RXD0 | SCI0 asynchronous serial interface | Full-duplex UART channel with programmable baud rate generator and LIN support |
| AN000–AN020 | Analog input channels | 21 dedicated 12-bit A/D input pins with shared reference (VREFH/VREFL) and temperature sensor input |
| DA0 / DA1 | Digital-to-analog outputs | Two buffered 10-bit voltage-output DACs, usable for analog waveform generation or sensor calibration |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | Single-precision IEEE-754 compliant FPU enables efficient math-intensive control algorithms without software emulation |
| IEC60730 safety support | On-chip CRC calculator, A/D self-diagnostic, IWDT, and oscillation-stop detection meet Class B functional safety requirements |
| Low-power operation | Four power modes (Sleep, All-module stop, Software standby, Deep software standby) with RTC backup and 500 µA/MHz active current |
| Flexible clock system | Multiple on-chip oscillators (LOCO, HOCO), PLL, subclock, and independent IWDT clock enable robust clock redundancy and dynamic frequency scaling |
| Peripheral module stop | Selective clock gating per peripheral allows fine-grained power optimization without CPU intervention |
| 5-V tolerant I/Os | 17 pins support 5 V logic levels - simplifies interface with legacy peripherals and level-shifting circuits |
Applications
| Industrial PLC Controller | Building Automation Gateway |
|---|---|
Use Scenario: Central logic unit in DIN-rail mounted programmable logic controllers managing discrete I/O, analog sensor inputs, and fieldbus communication. IC Role / Device Role / Timing Role: Real-time deterministic execution host with 100 MHz CPU, dual A/D converters for process monitoring, and CAN/SCI for Modbus RTU and Profibus DP slave interfacing. Use Value: 128 KB SRAM enables large ladder logic buffers; 1 MB flash stores firmware and configuration; 5-V-tolerant I/Os directly interface with 24 V industrial sensors. | Use Scenario: Edge gateway aggregating HVAC, lighting, and security subsystems across BACnet MS/TP, KNX, and LonWorks networks. IC Role / Device Role / Timing Role: Protocol translation hub using multiple SCI channels (LIN/UART/Smart Card modes) and CAN for legacy building bus integration. Use Value: Three CAN channels (32 mailboxes) support concurrent BACnet MS/TP over CAN and proprietary actuator control; RTC enables time-stamped event logging. |
| Medical Diagnostic Instrument | Factory Asset Monitor |
Use Scenario: Portable ultrasound or patient monitor requiring analog signal conditioning, waveform generation, and USB HID connectivity. IC Role / Device Role / Timing Role: Mixed-signal controller with 21-channel 12-bit A/D for multi-lead ECG acquisition, 2-channel 10-bit DAC for reference waveform synthesis, and USB 2.0 function controller for PC tethering. Use Value: On-chip temperature sensor (±1°C) enables thermal drift compensation; IEC60730 compliance supports Class II medical device certification. | Use Scenario: Wireless vibration/temperature sensor node deployed on motors, pumps, and conveyors for predictive maintenance. IC Role / Device Role / Timing Role: Low-power sensing node controller with 10-bit A/D for thermistor inputs, RTC for scheduled wake-up, and SCI/RSPI for SPI-based MEMS accelerometer interface. Use Value: Deep software standby mode draws <1 µA with RTC running; 32 KB data flash stores calibration coefficients and fault logs locally. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5631EDDFP#V0 | Same package (100-pin LQFP), identical peripherals, but with 2 MB flash and 256 KB SRAM | Requires larger firmware images or extended RAM buffers; not suitable where cost or footprint constraints favor 1 MB/128 KB configuration | Select when future firmware growth or complex real-time OS usage demands extra memory headroom |
| R5F5630WDDFP#V0 | Same 1 MB/128 KB configuration and package, but belongs to RX630 Group - lacks USB 2.0 function controller and has reduced SCI count (max 8 vs 13) | Not suitable for USB-connected devices; limited serial protocol flexibility in multi-interface gateways | Select only if USB functionality is unnecessary and lower BOM cost is prioritized over interface versatility |
Compared with R5F5631WDDFP#V0, R5F5631EDDFP#V0 offers scalable memory for evolving firmware, while R5F5630WDDFP#V0 reduces feature count to lower cost - making R5F5631WDDFP#V0 the optimal balance of USB-enabled connectivity, industrial-grade peripherals, and memory capacity for mid-tier embedded control.
Availability
R5F5631WDDFP#V0 is available at Aetrix Electronics and suitable for industrial PLCs, building automation gateways, medical diagnostic instruments, and factory asset monitors requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F5631WDDFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX631 Group is engineered for high-integrity industrial control applications demanding real-time responsiveness, functional safety compliance (IEC60730), and rich peripheral integration - without Ethernet overhead.
FAQ
What is the maximum operating frequency of the R5F5631WDDFP#V0?
The R5F5631WDDFP#V0 operates at a maximum system clock frequency of 100 MHz, delivering 165 DMIPS performance. This speed is sustained across its 1 MB flash and 128 KB SRAM with zero wait states, enabling deterministic real-time execution for industrial control loops and protocol stacks. The CPU core uses a 5-stage pipeline and supports dynamic voltage/frequency scaling within the 2.7–3.6 V supply range.
Does the R5F5631WDDFP#V0 include an Ethernet MAC?
No, the R5F5631WDDFP#V0 does not include an Ethernet MAC or associated EDMAC. It belongs to the RX631 Group, which omits Ethernet functionality present in the RX63N Group. This makes the R5F5631WDDFP#V0 appropriate for applications relying on CAN, USB, or serial fieldbuses instead of wired Ethernet - reducing complexity and cost where 10/100 Mbps networking is unnecessary.
What safety features does the R5F5631WDDFP#V0 provide for IEC60730 compliance?
The R5F5631WDDFP#V0 includes multiple hardware-assisted safety features required for IEC60730 Class B compliance: oscillation-stoppage detection for main/subclocks, on-chip CRC calculator (with three polynomials), independent watchdog timer (IWDT) with dedicated LOCO clock, self-diagnostic function for the 10-bit A/D converter, and frequency measurement capability via MTU/TPU modules - all verified in Renesas' functional safety documentation for the RX631 Group.
How many analog input channels does the R5F5631WDDFP#V0 support?
The R5F5631WDDFP#V0 supports 21 channels of 12-bit A/D conversion (S12ADa unit) and 8 channels of 10-bit A/D conversion (ADb unit), with shared sample-and-hold circuitry. These channels are accessible via dedicated ANxx pins and include dedicated inputs for the on-chip temperature sensor, enabling simultaneous monitoring of external sensors and internal die temperature with ±1°C accuracy.
Is the R5F5631WDDFP#V0 pin-compatible with other RX631 Group MCUs in the same package?
Yes, the R5F5631WDDFP#V0 is pin-compatible with all other RX631 Group devices in the PLQP0100KB-A (100-pin LQFP) package, including R5F5631EDDFP#V0 and R5F5630WDDFP#V0. Pin functions, power domains, and peripheral mappings are consistent across this package variant - allowing hardware reuse when scaling flash/SRAM or selecting alternate feature sets within the RX631 family.
R5F5631WDDFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 14x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5631WDDFP#V0 FAQ
1.How can I place an order for R5F5631WDDFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5631WDDFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5631WDDFP#V0 reliable?
The price and inventory of R5F5631WDDFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5631WDDFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F5631WDDFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5631WDDFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5631WDDFP#V0?
R5F5631WDDFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5631WDDFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5631WDDFP#V0?
For technical support, including R5F5631WDDFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5631WDDFP#V0 requirements.
6.How does Aetrix verify that R5F5631WDDFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F5631WDDFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5631WDDFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F5631WDDFP#V0?
All R5F5631WDDFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5631WDDFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5631WDDFP#V0 part is unused and in its original packaging.
Return procedure for R5F5631WDDFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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