Renesas R5F563NACDLK#U0
- Part No.:
- R5F563NACDLK#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F563NACDLK#U0.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 145TFLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563NACDLK#U0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 768 KB on-chip flash, 128 KB SRAM, and 32 KB data flash. It features 145-pin TFLGA (PTLG0145KA-A) packaging, operates from 2.7–3.6 V, supports -40 to +85°C, and targets industrial networking and embedded control applications requiring deterministic real-time performance and secure connectivity.
For engineers reviewing the R5F563NACDLK#U0 datasheet, R5F563NACDLK#U0 pinout, R5F563NACDLK#U0 application, or R5F563NACDLK#U0 equivalent, key selection criteria include its Ethernet MAC with MII/RMII support, USB 2.0 host/function/OTG capability, three CAN channels compliant with ISO11898-1, 21-channel 12-bit A/D converter, and AES-128/192/256 encryption via DEU - all within a compact 7×7 mm TFLGA package.
Technical Context
The R5F563NACDLK#U0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, supporting 165 DMIPS at 100 MHz and ultra-compact variable-length instructions. Its memory subsystem includes zero-wait-state 100 MHz flash and SRAM, plus background-programmable 32 KB data flash rated for 100,000 erase/write cycles.
Peripheral integration centers on deterministic real-time I/O: dual DMA controllers (DMAC + EXDMAC), 20+ timers including MTU2 and TPU for PWM and encoder capture, RTC with battery backup, and dedicated Ethernet DMA (EDMAC) with 2 KB TX/RX FIFOs - all coordinated by a 187-source interrupt controller (ICU).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS, IEEE-754 single-precision FPU |
| Memory | 768 KB on-chip flash (no wait states), 128 KB SRAM, 32 KB reprogrammable data flash (100k cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG, 3× CAN (ISO11898-1), 4× I²C (up to 1 Mbps), 13× SCI |
| Analog | 21-channel 12-bit A/D converter (1 µs conversion @ 50 MHz PCLK), 8-channel 10-bit A/D, 2× 10-bit D/A, on-die temperature sensor (±1°C) |
| Security & Timing | AES-128/192/256 encryption/decryption (ECB/CBC), RTC with calendar and time-capture, independent watchdog timer (IWDT) |
| Package & Environment | 145-pin TFLGA (PTLG0145KA-A), 7×7 mm, 0.5 mm pitch, -40 to +85°C operating range, 2.7–3.6 V supply |
Pinout & Package
Package: 145-pin Thin Fine-Pitch Land Grid Array (TFLGA), PTLG0145KA-A, 7×7 mm body, 0.5 mm pitch, 0.75 mm height, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated analog/digital power pins; AVCC0 and VREFH share same 2.7–3.6 V rail; decoupling critical for ADC/DAC accuracy |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables PLL-based 100 MHz system clock with ±0.5% stability over temp/voltage |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3u-compliant MDIO bus for PHY register access; requires external pull-up on MDIO |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII mode: 4-bit TX/RX data; RMII mode: 2-bit TX/RX + REF_CLK; pin multiplexing controlled via PMR registers |
| USB_VBUS / USB_ID | USB OTG detection | VBUS sensing enables host/peripheral role auto-detection; ID pin selects OTG function (host vs device mode) |
| AD0–AD20 | Analog input channels | 21 dedicated 12-bit A/D inputs; shared with GPIO; internal sample-and-hold enables simultaneous sampling across multiple channels |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC with EDMAC | Dedicated 2 KB TX/RX FIFO and descriptor-based DMA offloads 100 Mbps frame processing from CPU, enabling real-time protocol stack execution |
| USB 2.0 Host/Function/OTG | Single-port dual-role module with 2 KB on-chip RAM buffer supports CDC, HID, and mass storage classes without external memory |
| Three ISO11898-1 CAN Channels | 32-mailbox per channel with programmable acceptance filtering and timestamping; supports CAN FD-ready timing configuration |
| DEU AES Encryption Engine | Hardware-accelerated AES-128/192/256 in ECB/CBC modes reduces firmware overhead for secure boot, OTA updates, and encrypted communication |
| Real-Time Clock with Battery Backup | RTC retains calendar/time during deep software standby using VBATT (2.3–3.6 V); supports alarm, periodic, and carry interrupts for low-power scheduling |
Applications
| Industrial Ethernet Gateway | Secure IoT Edge Controller |
|---|---|
Use Scenario: Protocol translation between Modbus RTU field devices and cloud-connected Ethernet backbone in factory automation. IC Role / Device Role / Timing Role: Primary MCU executing real-time Modbus stack, managing Ethernet TCP/IP offload via EDMAC, and synchronizing time-stamped sensor logs via RTC. Use Value: Integrated Ethernet MAC + USB + CAN eliminates external PHY and bridge ICs; 768 KB flash accommodates dual-application firmware images for fail-safe updates. |
Use Scenario: Smart meter with tamper detection, encrypted firmware updates, and local HMI via USB-CDC interface. IC Role / Device Role / Timing Role: System-on-chip handling metrology A/D sampling, AES-encrypted OTA decryption, and USB host-mode firmware validation. Use Value: On-chip DEU accelerates AES-256 decryption by >10× vs software; 128 KB SRAM buffers full firmware image before flash programming. |
| Medical Patient Monitor | Automotive Diagnostic Tool |
Use Scenario: Portable vital-sign monitor acquiring ECG, SpO₂, and temperature data while transmitting alerts over Ethernet/WiFi bridge. IC Role / Device Role / Timing Role: Real-time acquisition controller using 21-channel A/D with sample-and-hold, synchronized to MTU2 PWM for LED drive timing. Use Value: ±1°C on-die temperature sensor calibrates analog front-end drift; 100 MHz CPU ensures sub-millisecond response to arrhythmia detection algorithms. |
Use Scenario: Handheld OBD-II scanner reading vehicle CAN bus diagnostics and displaying results via USB-connected tablet. IC Role / Device Role / Timing Role: CAN protocol interpreter with 32-mailbox filtering, USB CDC bridge, and real-time fault logging to data flash. Use Value: Three independent CAN modules enable concurrent J1939, ISO15765, and proprietary bus monitoring; 32 KB data flash stores 10,000+ diagnostic events with wear leveling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDLK#U0 | 2 MB flash, same 145-pin TFLGA package, identical peripheral set and clock specs | Requires larger firmware footprint; suitable when bootloader, crypto keys, and application require >768 KB code space | Select when future firmware expansion or dual-bank secure update is required; no PCB change needed |
| R5F563NACDFC#U0 | LQFP-176 package (PLQP0176KB-A), same 768 KB flash/SRAM, adds external bus interface (32-bit, 50 MHz) | Enables connection to external SDRAM or NOR flash; higher pin count increases board area and routing complexity | Choose for designs needing external memory expansion; requires layout revision due to package and pinout differences |
Compared with R5F563NACDLK#U0, R5F563NECDLK#U0 offers 128% more flash for complex protocol stacks without changing footprint, while R5F563NACDFC#U0 trades compact TFLGA size for external memory bandwidth - making the former ideal for firmware scalability and the latter for memory-intensive HMI or data logging.
Availability
R5F563NACDLK#U0 is available at Aetrix Electronics and suitable for industrial gateways, medical edge devices, automotive diagnostics tools, and secure IoT controllers requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for R5F563NACDLK#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX63N Group, including R5F563NACDLK#U0, was designed for deterministic real-time embedded systems requiring integrated Ethernet, USB, CAN, and hardware security - targeting industrial automation, building control, and medical equipment where reliability and peripheral integration are critical.
FAQ
What is the maximum operating frequency and core architecture of the R5F563NACDLK#U0?
The R5F563NACDLK#U0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with a 5-stage CISC Harvard pipeline. It delivers 165 DMIPS and includes a single-precision IEEE-754 floating-point unit, 32-bit multiplier (1-cycle execution), and 32-bit divider (2-cycle execution). This architecture enables deterministic real-time performance for industrial control and protocol stack execution in the R5F563NACDLK#U0.
Does the R5F563NACDLK#U0 support Ethernet connectivity, and what interfaces are available?
Yes, the R5F563NACDLK#U0 integrates a full IEEE 802.3-compliant Ethernet MAC supporting both 10 and 100 Mbps operation in full- and half-duplex modes. It supports MII (Media Independent Interface) and RMII (Reduced MII) physical layer interfaces, Magic Packet™ wake-on-LAN, and IEEE 802.3x flow control. The dedicated EDMAC controller with 2 KB TX/RX FIFOs enables efficient descriptor-based packet handling in the R5F563NACDLK#U0.
What are the memory resources available on the R5F563NACDLK#U0?
The R5F563NACDLK#U0 includes 768 KB of on-chip flash memory (zero wait states at 100 MHz), 128 KB of SRAM (also zero wait states), and 32 KB of data flash rated for 100,000 erase/write cycles. Flash supports on-board programming and background operations, while SRAM provides unified instruction/operand space and deep software standby backup capability - all integral to the R5F563NACDLK#U0's real-time embedded functionality.
How many communication interfaces does the R5F563NACDLK#U0 support, and which protocols are included?
The R5F563NACDLK#U0 supports Ethernet MAC, USB 2.0 host/function/OTG, three CAN 2.0B channels (ISO11898-1 compliant), four I²C interfaces (one FM+, up to 1 Mbps), 13 serial communications interfaces (SCI) with flexible modes (asynchronous, SPI/I²C emulation, LIN), three RSPI channels, one IEBus channel, and a parallel data capture unit (PDC). These interfaces are fully integrated and independently clocked in the R5F563NACDLK#U0.
What security and analog features are built into the R5F563NACDLK#U0?
The R5F563NACDLK#U0 includes a Data Encryption Unit (DEU) supporting AES-128/192/256 encryption/decryption in ECB and CBC modes, a 21-channel 12-bit A/D converter with sample-and-hold and 1 µs conversion time, an 8-channel 10-bit A/D converter, two 10-bit D/A channels, and an on-die temperature sensor accurate to ±1°C. These features provide hardware-accelerated security and high-fidelity analog signal acquisition in the R5F563NACDLK#U0.
R5F563NACDLK#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NACDLK#U0 FAQ
1.How can I place an order for R5F563NACDLK#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NACDLK#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NACDLK#U0 reliable?
The price and inventory of R5F563NACDLK#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NACDLK#U0 is usually 5 days.
3.What payment methods are accepted for R5F563NACDLK#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NACDLK#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NACDLK#U0?
R5F563NACDLK#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NACDLK#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NACDLK#U0?
For technical support, including R5F563NACDLK#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NACDLK#U0 requirements.
6.How does Aetrix verify that R5F563NACDLK#U0 is sourced from the original manufacturer or authorized distributors?
All R5F563NACDLK#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NACDLK#U0 meets industry standards.
7.What is the process for return or replacement of R5F563NACDLK#U0?
All R5F563NACDLK#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NACDLK#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NACDLK#U0 part is unused and in its original packaging.
Return procedure for R5F563NACDLK#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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