Renesas R5F563NADDLK#U0
- Part No.:
- R5F563NADDLK#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F563NADDLK#U0.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,203
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563NADDLK#U0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision FPU, 768 KB on-chip flash, 128 KB SRAM, 32 KB data flash, and hardware AES encryption. It features 145-pin TFLGA (PTLG0145KA-A) packaging, operates from 2.7–3.6 V, supports -40 to +85°C, and targets industrial networking and embedded control applications requiring real-time connectivity and secure firmware updates.
For engineers reviewing the R5F563NADDLK#U0 datasheet, R5F563NADDLK#U0 pinout, R5F563NADDLK#U0 application, or R5F563NADDLK#U0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 12-bit/10-bit ADC channel count (21/8), dual 10-bit DACs, USB 2.0 host/function/OTG capability, and IEC60730 safety features including CRC, self-diagnostic A/D, and oscillation-stop detection.
Technical Context
The R5F563NADDLK#U0 implements the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-delivering 165 DMIPS at 100 MHz. It integrates dedicated peripherals including an Ethernet controller (ETHERC) with 2 KB TX/RX FIFOs, EDMAC for descriptor-based DMA offload, and a USB 2.0 host/function module supporting full-speed (12 Mbps) OTG operation.
Its memory subsystem includes no-wait-state 100 MHz flash (768 KB), 128 KB SRAM with deep software standby backup, and 32 KB reprogrammable data flash (100,000 erase/write cycles). Clock management supports external crystal (4–16 MHz), internal HOCO/LOCO, PLL synthesis, and independent IWDT clock source.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RX 32-bit CISC CPU with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Frequency | 100 MHz system clock (ICLK); peripheral clock (PCLK) up to 50 MHz |
| Memory | 768 KB flash (no wait states), 128 KB SRAM, 32 KB data flash (100k cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG, 3× CAN, 4× I²C (1× FM+), 13× SCI, 3× RSPI |
| Analog | 21-channel 12-bit ADC (1 µs conversion), 8-channel 10-bit ADC, 2× 10-bit DAC, on-die temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256 (ECB/CBC), CRC calculator, IEC60730-compliant self-diagnostic A/D, oscillation-stop detection |
| Package | 145-pin TFLGA (PTLG0145KA-A), 7 × 7 mm, 0.5 mm pitch, 5-V tolerant I/O (18 pins) |
Pinout & Package
Package: 145-pin Thin Fine-Pitch Land Grid Array (TFLGA), PTLG0145KA-A, 7 × 7 mm body, 0.5 mm pitch, 0.7 mm height, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated power domains for core (VCC), analog (AVCC0/VREFH), USB (VCC_USB), and battery backup (VBATT) |
| XTAL / EXTAL | Main clock oscillator input/output | Supports 4–16 MHz crystal; enables precise timing for Ethernet, USB, and RTC |
| MDIO / MDC | Management Data Input/Output | IEEE 802.3-compliant PHY register access interface for Ethernet configuration |
| TXD[3:0] / RXD[3:0] | Ethernet transmit/receive data | MII interface signals; RMII mode uses TXD[1:0]/RXD[1:0] plus REF_CLK |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) physical layer interface; supports host, function, and OTG roles |
| AD[20:0] | 12-bit analog input channels | 21 dedicated pins for high-accuracy sensing; includes internal sample-and-hold and reference voltage generation |
| DA[1:0] | 10-bit DAC output | Two buffered analog outputs (0–VREFH range); usable for waveform generation or sensor biasing |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Hardware-accelerated 10/100 Mbps frame handling with descriptor-based DMA reduces CPU load by >70% in TCP/IP stack execution |
| USB 2.0 Host/Function/OTG | Single-port dual-role controller with 2 KB on-chip RAM buffer enables seamless device enumeration and host-side peripheral attachment without external memory |
| IEC60730 Safety Support | Integrated CRC calculator, A/D self-test, clock monitoring, and IWDT with dedicated oscillator meet Class B functional safety requirements out-of-the-box |
| Floating-Point Unit | IEEE-754 single-precision FPU enables deterministic real-time math (e.g., motor control algorithms, sensor fusion) without software emulation overhead |
| Flexible Clock System | Independent programmable dividers/multipliers for ICLK, PCLK, FCLK, and BCLK allow optimal power/performance trade-offs per subsystem (e.g., 100 MHz CPU + 50 MHz peripherals + 50 MHz bus) |
Applications
| Industrial Ethernet Gateway | Secure IoT Edge Controller |
|---|---|
|
Use Scenario: Protocol translation between Modbus RTU field devices and cloud-connected Ethernet backbone. IC Role / Device Role / Timing Role: Primary MCU executing real-time protocol stack, managing dual Ethernet/serial interfaces, and performing time-critical packet forwarding. Use Value: Integrated ETHERC + EDMAC eliminates external PHY and DMA controller, reducing BOM cost by $1.80 and PCB area by 22 mm² vs. discrete solutions. |
Use Scenario: Smart building node aggregating sensor data (temp, humidity, occupancy) and transmitting encrypted payloads via TLS over Ethernet. IC Role / Device Role / Timing Role: Secure application processor running lightweight RTOS, performing AES-128 encryption, and managing battery-backed RTC for time-stamped logs. Use Value: On-chip DEU accelerates AES-CBC by 12× vs. software-only implementation, enabling 256-byte payload encryption in <120 µs while preserving CPU bandwidth for sensor polling. |
| Programmable Logic Controller (PLC) I/O Module | Medical Diagnostic Interface |
|
Use Scenario: DIN-rail mounted I/O expansion unit with isolated digital inputs, analog current loops, and EtherCAT slave interface. IC Role / Device Role / Timing Role: Deterministic real-time controller synchronizing I/O sampling (via TPU-triggered ADC) and EtherCAT frame transmission with <1 µs jitter. Use Value: MTU2/TPU timer units provide hardware-synchronized PWM and capture with phase-counting mode-enabling precise 4–20 mA loop calibration without external timing ICs. |
Use Scenario: Portable ultrasound front-end interfacing with transducer arrays and digitizing RF echo signals. IC Role / Device Role / Timing Role: High-speed data acquisition controller using PDC to capture parallel image sensor output and DMA to stream to external SDRAM. Use Value: Parallel Data Capture Unit (PDC) supports direct transfer of 16-bit pixel data at up to 20 MSPS into internal RAM or CS space-eliminating FPGA glue logic in mid-tier diagnostic tools. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDLK#U0 | Same package (145-pin TFLGA), 2 MB flash (vs. 768 KB), identical peripheral set and speed grade | Preferred for firmware-rich applications requiring OTA update partitioning or large bootloader + application separation | Select when >1 MB code space is needed; retains full pin and software compatibility |
| R5F563NBDDLK#U0 | Same package, 1 MB flash, same RAM/data flash, but reduced peripheral count: only 2 CAN channels (vs. 3), no PDC, fewer SCI channels | Suitable for cost-sensitive industrial HMI or basic gateway designs without image capture or multi-bus CAN requirements | Choose for lower-cost BOM where Ethernet, USB, and 12-bit ADC remain essential but PDC/CAN3 are unused |
Compared with R5F563NADDLK#U0, R5F563NEDDLK#U0 offers scalable flash headroom for future feature expansion without layout changes, while R5F563NBDDLK#U0 reduces silicon cost by disabling non-critical modules-enabling tiered product families with shared PCB design and toolchain.
Availability
R5F563NADDLK#U0 is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, and secure IoT edge devices requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563NADDLK#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX63N Group is designed for high-integrity networked embedded systems-integrating Ethernet, USB, security, and real-time control in a single chip to reduce system complexity and accelerate time-to-market for industrial gateways and smart sensors.
FAQ
What is the maximum operating frequency and core performance of the R5F563NADDLK#U0?
The R5F563NADDLK#U0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using its 32-bit RX CPU core with 5-stage pipeline and variable-length instruction set. Its single-precision IEEE-754 FPU enables deterministic floating-point math critical for motor control and sensor fusion algorithms within the R5F563NADDLK#U0's real-time execution environment.
Does the R5F563NADDLK#U0 support Ethernet connectivity, and what interface modes are available?
Yes, the R5F563NADDLK#U0 integrates a full IEEE 802.3-compliant Ethernet MAC supporting both 10 Mbps and 100 Mbps operation in full- and half-duplex modes. It provides MII (Media Independent Interface) and RMII (Reduced MII) physical layer options, along with MDIO/MDC management interface and Magic Packet™ wake-on-LAN capability-all implemented in hardware within the R5F563NADDLK#U0 die.
What analog capabilities does the R5F563NADDLK#U0 offer for sensor interfacing?
The R5F563NADDLK#U0 includes a 21-channel 12-bit A/D converter with 1 µs conversion time (at 50 MHz PCLK), an 8-channel 10-bit A/D converter, two 10-bit D/A converters, and an on-die temperature sensor accurate to ±1°C. These resources are directly accessible via dedicated pins and support hardware-triggered conversions using MTU2/TPU timers-key for synchronized sensing in the R5F563NADDLK#U0's industrial applications.
Is the R5F563NADDLK#U0 suitable for IEC60730 Class B safety-certified designs?
Yes, the R5F563NADDLK#U0 includes multiple hardware features required for IEC60730 Class B compliance: oscillation-stop detection, clock frequency measurement (MCK), CRC calculator with three polynomials, independent watchdog timer (IWDT) with dedicated LOCO clock, and self-diagnostic capability for the 10-bit A/D converter-all documented in the R5F563NADDLK#U0's functional safety manual (R01DS0098EJ).
What package type and pin count does the R5F563NADDLK#U0 use?
The R5F563NADDLK#U0 is housed in a 145-pin Thin Fine-Pitch Land Grid Array (TFLGA) package, designated PTLG0145KA-A, measuring 7 × 7 mm with 0.5 mm pitch. It provides 111 general-purpose I/O pins (including 18 with 5-V tolerance), and its pinout is fully compatible with other RX63N Group devices in the same package family-including the R5F563NADDLK#U0's support for Ethernet, USB, CAN, and parallel data capture functions.
R5F563NADDLK#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NADDLK#U0 FAQ
1.How can I place an order for R5F563NADDLK#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NADDLK#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NADDLK#U0 reliable?
The price and inventory of R5F563NADDLK#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NADDLK#U0 is usually 5 days.
3.What payment methods are accepted for R5F563NADDLK#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NADDLK#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NADDLK#U0?
R5F563NADDLK#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NADDLK#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NADDLK#U0?
For technical support, including R5F563NADDLK#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NADDLK#U0 requirements.
6.How does Aetrix verify that R5F563NADDLK#U0 is sourced from the original manufacturer or authorized distributors?
All R5F563NADDLK#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NADDLK#U0 meets industry standards.
7.What is the process for return or replacement of R5F563NADDLK#U0?
All R5F563NADDLK#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NADDLK#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NADDLK#U0 part is unused and in its original packaging.
Return procedure for R5F563NADDLK#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563NADDLK#U0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
