Renesas R5F563NADGFP#V0
- Part No.:
- R5F563NADGFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563NADGFP#V0.pdf
- Description:
- 32BIT MCU RX63N
- Quantity:
- Payment:

- Shipping:

Inventory:2,145
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563NADGFP#V0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 768 KB on-chip flash, 128 KB SRAM, and 32 KB data flash. It features 10- and 12-bit A/D converters (21+8 channels), dual 10-bit D/A outputs, RTC with battery backup, and AES encryption (DEU). Used in industrial gateways requiring deterministic real-time control, networked HMI, and secure firmware updates.
For engineers reviewing the R5F563NADGFP#V0 datasheet, R5F563NADGFP#V0 pinout, R5F563NADGFP#V0 application, or R5F563NADGFP#V0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 100 MHz CPU performance (165 DMIPS), 176-pin LQFP package with 134 GPIOs (18× 5-V tolerant), and IEC60730 safety features including CRC, IWDT, and A/D self-diagnostic.
Technical Context
The R5F563NADGFP#V0 implements the 32-bit RX CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code and fast interrupt response. It integrates dedicated hardware accelerators: a 32×32→64-bit multiplier (1-cycle), 32/32→32 divider (2-cycle), and barrel shifter, all operating at full 100 MHz system clock.
Its peripheral subsystem includes an Ethernet controller (10/100 Mbps, MII/RMII), three CAN modules (ISO11898-1 compliant, 32 mailboxes each), 13 SCI channels supporting UART/I²C/SPI/LIN modes, four I²C interfaces (up to 1 Mbps), and a parallel data capture unit (PDC) for image sensor interfacing-all synchronized to independent clock domains (ICLK/PCLK/FCLK/BCLK).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RX 32-bit CPU, 100 MHz max, 165 DMIPS, IEEE-754 single-precision FPU |
| Memory | 768 KB flash (no wait states @100 MHz), 128 KB SRAM, 32 KB reprogrammable data flash (100k cycles) |
| Analog | 21×12-bit + 8×10-bit A/D converters (1 µs/ch @50 MHz PCLK), 2×10-bit D/A, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), 3× CAN, 13× SCI, 4× I²C (1 Mbps), 3× RSPI, USB 2.0 host/function/OTG |
| Timers & Control | 16× TPU channels, 6× MTU2 channels, 4× TMR, 4× CMT, RTC with alarm/carry interrupts and time-capture |
| Security & Safety | AES-128/192/256 (ECB/CBC), CRC calculator (3 polynomials), IWDT, oscillation-stop detection, A/D self-diagnostic |
| Package & Environment | LQFP-176 (PLQP0176KB-A, 24×24 mm, 0.5 mm pitch), -40 to +85°C (D version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 mm × 24 mm, 0.5 mm pitch, exposed pad (thermal pad), RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | 2.7–3.6 V core/analog supply; 13 dedicated VCC/VSS pairs ensure low-noise operation across high-speed digital and analog domains |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables precise timing for Ethernet, USB, and RTC; PLL locks to generate 100 MHz ICLK |
| ETH_MDC / ETH_MDIO | MDIO management interface | IEEE 802.3-compliant serial management bus for PHY configuration and status monitoring |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII mode: 4-bit TX/RX data; RMII mode: 2-bit TX/RX + REF_CLK; supports full/half-duplex and flow control (802.3x) |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical interface | Full-speed (12 Mbps) transceiver with integrated pull-up; VBUS sensing enables host/device role negotiation and OTG support |
| AD0–AD20 / AD0–AD7 | Analog input channels | Dedicated pins for 21×12-bit and 8×10-bit A/D; internal sample-and-hold enables simultaneous sampling across multiple channels |
| DA0 / DA1 | Digital-to-analog outputs | 10-bit voltage-output DACs referenced to VREFH (2.7–3.6 V); used for analog waveform generation or sensor calibration signals |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC with EDMAC | Dedicated DMA engine (EDMAC) offloads CPU via descriptor-based packet handling; 2 KB TX/RX FIFOs enable zero-copy streaming for TCP/IP stacks |
| IEC60730-compliant safety suite | Integrated oscillation-stop detection, CRC calculator (8/16-bit), IWDT with dedicated LOCO clock, and A/D converter self-test reduce external safety component count |
| Flexible clock domain control | Independent programmable dividers/multipliers for ICLK (CPU), PCLK (peripherals), FCLK (FlashIF), and BCLK (external bus) enable precise power/performance tuning |
| High-density GPIO with configurability | 134 general-purpose I/O pins (18× 5-V tolerant), open-drain capability, software-selectable drive strength, and 8-bit port switching simplify PCB routing and legacy interface adaptation |
| Secure firmware execution | Data Encryption Unit (DEU) performs AES-128/192/256 encryption/decryption in ECB/CBC modes; supports secure boot and OTA update integrity verification |
Applications
| Industrial Ethernet Gateway | Networked Human-Machine Interface (HMI) |
|---|---|
Use Scenario: Protocol translation between Modbus RTU field devices and cloud-connected Ethernet backbone in factory automation. IC Role / Device Role / Timing Role: Primary MCU executing real-time Modbus stack, managing Ethernet frame assembly/disassembly, and synchronizing timestamped I/O events via RTC and timer-triggered A/D conversion. Use Value: Integrated Ethernet MAC + 100 MHz CPU eliminates external PHY and reduces latency to <50 µs for deterministic cycle times; 768 KB flash accommodates dual-application images for safe firmware updates. |
Use Scenario: Touch-enabled panel PC controlling HVAC, lighting, and access systems in commercial buildings. IC Role / Device Role / Timing Role: Central controller interfacing capacitive touch overlay (via SCI/I²C), driving LCD via PDC, and managing secure remote diagnostics over Ethernet. Use Value: PDC enables direct image sensor or display data transfer without CPU intervention; AES-DEU secures OTA firmware patches; 134 GPIOs support multi-channel relay and sensor expansion. |
| Smart Energy Metering Hub | Secure IoT Edge Node |
Use Scenario: Multi-tenant energy aggregation node collecting submeter data via RS485 and reporting via Ethernet/WAN to utility SCADA. IC Role / Device Role / Timing Role: Time-synchronized data concentrator using RTC alarm interrupts and TPU-captured pulse inputs from mechanical meters; performs CRC-verified data logging to internal flash. Use Value: RTC battery backup ensures time continuity during main power loss; 12-bit A/D with sample-and-hold enables accurate voltage/current sampling at 1 kHz; DEU encrypts meter readings before transmission. |
Use Scenario: Field-deployed environmental monitor aggregating sensor data (temp, humidity, CO₂) and transmitting encrypted payloads over Ethernet to edge gateway. IC Role / Device Role / Timing Role: Low-power sensor fusion hub using deep software standby mode (RTC wake-up), on-die temperature sensor calibration, and AES-encrypted data packaging. Use Value: Four low-power modes (including deep software standby) achieve <500 µA/MHz active current; integrated temperature sensor (±1°C) enables on-chip calibration of external sensors without extra components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDFC | Same RX63N Group, identical 176-pin LQFP package, but with 2 MB flash and 256 KB SRAM (vs. 768 KB/128 KB) | Requires larger memory footprint for complex protocol stacks or GUI rendering; higher BOM cost where 768 KB suffices | Select when firmware size exceeds 768 KB or additional SRAM is needed for large buffers or multitasking OS |
| R5F563NADDFC | Identical flash/SRAM configuration (768 KB/128 KB) and package, but D version with same -40 to +85°C rating; differs only in traceability marking and screening batch | No functional difference; intended for alternate distribution channels or specific OEM sourcing requirements | Use as drop-in replacement where identical electrical and thermal specs are required and supply chain diversification is needed |
Compared with R5F563NADGFP#V0, R5F563NECDFC offers expanded memory for feature-rich firmware, while R5F563NADDFC provides identical functionality with alternate logistics traceability-neither requires PCB or firmware changes.
Availability
R5F563NADGFP#V0 is available at Aetrix Electronics and suitable for industrial gateways, networked HMIs, and smart energy metering hubs requiring stable component supply, long-term lifecycle support, and automotive-grade reliability under extended temperature operation.
Supply support for R5F563NADGFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX63N Group targets industrial automation and networked embedded systems, integrating Ethernet, USB, CAN, and safety features into a single high-performance 32-bit MCU platform optimized for deterministic real-time control and secure connectivity.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563NADGFP#V0?
The R5F563NADGFP#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance. Its RX CPU core includes a single-precision IEEE-754 floating-point unit, 32×32→64-bit multiplier (1-cycle execution), and 32/32→32 divider (2-cycle execution), enabling efficient real-time signal processing and control loop execution in the R5F563NADGFP#V0.
Does the R5F563NADGFP#V0 support Ethernet connectivity, and what interface standards does it implement?
Yes, the R5F563NADGFP#V0 integrates a full-featured Ethernet MAC supporting both 10 and 100 Mbps operation in full- and half-duplex modes. It implements IEEE 802.3-compliant MII and RMII physical layer interfaces, includes Magic Packet™ wake-on-LAN detection, and complies with IEEE 802.3x flow control-making the R5F563NADGFP#V0 suitable for industrial Ethernet nodes without external PHY dependency.
What are the memory resources available on the R5F563NADGFP#V0?
The R5F563NADGFP#V0 includes 768 KB of on-chip flash memory (executed at 100 MHz with zero wait states), 128 KB of SRAM (also zero-wait), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. This memory configuration supports robust firmware partitioning, background data logging, and real-time buffer allocation-key capabilities for reliable operation in the R5F563NADGFP#V0.
How does the R5F563NADGFP#V0 support functional safety compliance for industrial applications?
The R5F563NADGFP#V0 includes built-in features aligned with IEC60730 Class B requirements: oscillation-stoppage detection, hardware CRC calculator (with three selectable polynomials), independent watchdog timer (IWDT) driven by a dedicated 125-kHz LOCO clock, and self-diagnostic capability for the 10-bit A/D converter. These features reduce external safety circuitry and accelerate certification for the R5F563NADGFP#V0 in safety-critical industrial designs.
What package type and pin count does the R5F563NADGFP#V0 use, and what are its key I/O characteristics?
The R5F563NADGFP#V0 uses a 176-pin LQFP package (PLQP0176KB-A, 24 mm × 24 mm, 0.5 mm pitch) with 134 general-purpose I/O pins. Of these, 18 pins are 5-V tolerant, all support software-configurable pull-up resistors and open-drain output, and drive strength is selectable per port-providing flexible interfacing to legacy peripherals, sensors, and actuators in the R5F563NADGFP#V0.
R5F563NADGFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 14x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NADGFP#V0 FAQ
1.How can I place an order for R5F563NADGFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NADGFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NADGFP#V0 reliable?
The price and inventory of R5F563NADGFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NADGFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NADGFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NADGFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NADGFP#V0?
R5F563NADGFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NADGFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NADGFP#V0?
For technical support, including R5F563NADGFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NADGFP#V0 requirements.
6.How does Aetrix verify that R5F563NADGFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NADGFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NADGFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NADGFP#V0?
All R5F563NADGFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NADGFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NADGFP#V0 part is unused and in its original packaging.
Return procedure for R5F563NADGFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563NADGFP#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

