Renesas R5F563NBCDBG#G0
- Part No.:
- R5F563NBCDBG#G0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F563NBCDBG#G0.pdf
- Description:
- RX63N MCU 1MB/128KB 176BGA 0.8MM
- Quantity:
- Payment:

- Shipping:

Inventory:2,301
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563NBCDBG#G0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 1 Mbyte on-chip flash, 128 Kbytes SRAM, and 32 Kbytes data flash. It operates from a 2.7–3.6 V supply, supports -40 to +105°C (G version), and targets industrial networking, gateway, and embedded control applications requiring deterministic real-time performance and secure connectivity.
For engineers reviewing the R5F563NBCDBG#G0 datasheet, R5F563NBCDBG#G0 pinout, R5F563NBCDBG#G0 application, or R5F563NBCDBG#G0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 100-MHz deterministic timing, AES-128/192/256 encryption via DEU, 12-bit A/D converter with 21 channels, and 134 general-purpose I/O pins with 5-V tolerance.
Technical Context
The R5F563NBCDBG#G0 implements the CISC Harvard-architecture RX CPU core with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU). It integrates dedicated hardware accelerators including a DMA controller (4 channels), EXDMA (2 channels), DTC, and EDMAC for Ethernet-enabling zero-copy frame handling at 100 Mbps full-duplex.
Its clock system combines external crystal oscillator (4–16 MHz), internal PLL, 50-MHz HOCO, and 125-kHz LOCO, with independent frequency division for ICLK (up to 100 MHz), PCLK (up to 50 MHz), FCLK (up to 50 MHz), and BCLK (up to 50 MHz). The device includes dual A/D converters (12-bit ×21 ch, 10-bit ×8 ch), 2×10-bit D/A, RTC with battery backup, and CRC calculator compliant with IEC60730 Class B.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard architecture with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK); enables deterministic real-time execution and 1-μs A/D conversion time |
| Memory | 1 Mbyte flash (no wait states @ 100 MHz), 128 Kbytes SRAM (no wait states), 32 Kbytes reprogrammable data flash (100,000 cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG, CAN (3 channels, ISO11898-1), 4× I²C (1 Mbps), 13× SCI, 3× RSPI |
| Analog Peripherals | 12-bit A/D converter (21 channels, 1.0 μs conversion), 10-bit A/D (8 channels), 2×10-bit D/A, on-chip temperature sensor (±1°C) |
| Security & Safety | Data Encryption Unit (AES-128/192/256, ECB/CBC), CRC calculator (3 polynomials), MPU, IEC60730 self-diagnostic functions |
| Package & Environment | LFBGA-176 (PLBG0176GA-A, 13 × 13 mm, 0.8-mm pitch), operating temperature −40 to +105°C (G version) |
Pinout & Package
Package: PLBG0176GA-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 13 × 13 mm body, 0.8 mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated power domains for core (VCC), analog (AVCC0), USB (VCC_USB), and reference (VREFH); decoupling required per Renesas layout guidelines |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables precise timing for Ethernet MAC, USB, and RTC synchronization |
| MDIO / MDC | Management Data Input/Output | IEEE 802.3-compliant PHY management interface for Ethernet configuration and status monitoring |
| TXD[3:0] / RXD[3:0] | Ethernet transmit/receive data | MII interface signals; RMII mode uses TXD[1:0]/RXD[1:0] plus TX_EN, CRS_DV, REF_CLK |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) USB transceiver interface; supports host, function, and OTG operation with integrated 2-KB buffer RAM |
| AD[20:0] | Analog input channels | 21-channel 12-bit A/D inputs with sample-and-hold; AN000–AN020 mapped to physical pins per LFBGA-176 pinout diagram |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC with EDMAC | Hardware-accelerated descriptor-based DMA offloads CPU; 2-KB TX/RX FIFOs enable sustained 100 Mbps throughput without CPU intervention |
| Floating-Point Unit (FPU) | Single-precision IEEE-754 compliant; enables real-time motor control, sensor fusion, and digital signal processing without software emulation overhead |
| Flexible Clock Architecture | Independent programmable dividers for ICLK, PCLK, FCLK, BCLK allow optimal peripheral clocking-e.g., 100 MHz for CPU, 50 MHz for A/D, 25 MHz for USB |
| IEC60730 Safety Support | Integrated oscillation-stop detection, CRC calculator, IWDT, and A/D self-diagnostic reduce certification effort for Class B appliance and industrial control systems |
| Secure Boot & Encryption | DEU provides hardware AES acceleration; unique 16-byte ID (G version) enables secure device authentication and firmware binding |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
|
Use Scenario: Aggregates Modbus TCP, CANopen, and BACnet MS/TP traffic across fieldbus networks into unified Ethernet backbone. IC Role / Device Role / Timing Role: Primary protocol translation MCU with deterministic Ethernet MAC, multi-protocol stack execution, and timestamped packet handling. Use Value: 100 MHz RX core + EDMAC ensures sub-100 μs interrupt latency and jitter-free frame scheduling for time-critical automation protocols. |
Use Scenario: Manages metrology ICs, PLC I/O, and wireless modules in DIN-rail-mounted energy gateways for AMI deployments. IC Role / Device Role / Timing Role: Central controller with simultaneous A/D sampling (21-channel 12-bit), secure firmware updates (AES), and RTC-backed event logging. Use Value: On-chip 128 Kbytes SRAM buffers high-rate metering data; DEU enables OTA firmware signing verified at boot. |
| Factory Automation Controller | Building Management System (BMS) Node |
|
Use Scenario: Real-time motion control node coordinating servo drives, safety I/O, and HMI over EtherCAT or PROFINET. IC Role / Device Role / Timing Role: Deterministic real-time MCU with MTU2/TPU timers for PWM generation, encoder capture, and synchronized I/O update. Use Value: 16-bit MTU2 (6 channels) and TPU (12 channels) deliver <100 ns phase resolution for multi-axis servo coordination. |
Use Scenario: Distributed HVAC controller interfacing temperature/humidity sensors, valve actuators, and CO₂ monitors via I²C, SCI, and analog inputs. IC Role / Device Role / Timing Role: Sensor fusion hub with integrated 12-bit A/D (21 ch), 10-bit D/A (2 ch), and RTC for scheduled ventilation control. Use Value: Single-chip integration eliminates external ADC/DAC and reduces BOM cost by 30% versus discrete analog front-end solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDBG#G0 | 2 Mbyte flash, same 128 Kbytes SRAM, identical LFBGA-176 package and peripheral set | Higher code storage capacity for complex protocol stacks (e.g., TLS, MQTT-SN) or dual-application firmware images | Select when >1 Mbyte flash is required for feature-rich firmware or future-proofing; pin-compatible with no layout change |
| R5F563NBCDFC#G0 | LQFP-176 package (PLQP0176KB-A), same 1 Mbyte flash/128 Kbytes SRAM/peripherals, but 0.5-mm pitch vs. 0.8-mm pitch | Preferred for prototyping, manual assembly, or cost-sensitive production where BGA rework is undesirable | Choose for easier PCB assembly or test access; requires board redesign due to different footprint and thermal pad requirements |
Compared with R5F563NBCDBG#G0, R5F563NECDBG#G0 offers double flash capacity for advanced networking stacks, while R5F563NBCDFC#G0 trades BGA density for LQFP manufacturability-neither alters core timing, security, or analog capabilities.
Availability
R5F563NBCDBG#G0 is available at Aetrix Electronics and suitable for industrial gateways, smart metering hubs, and factory automation controllers requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature resilience.
Supply support for R5F563NBCDBG#G0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group is designed for high-performance, safety-certifiable embedded applications demanding real-time Ethernet connectivity, cryptographic security, and rich analog integration-targeting industrial automation, building control, and energy infrastructure.
FAQ
What is the maximum operating frequency of the R5F563NBCDBG#G0?
The R5F563NBCDBG#G0 operates at a maximum system clock frequency of 100 MHz. This enables 165 DMIPS performance and supports real-time tasks such as 100 Mbps Ethernet frame processing, 12-bit A/D conversion in 1.0 μs, and deterministic interrupt response under 100 ns jitter. The CPU core maintains full functionality-including FPU and MPU-at this frequency with no wait states on flash or SRAM.
Does the R5F563NBCDBG#G0 include an Ethernet MAC, and what interfaces does it support?
Yes, the R5F563NBCDBG#G0 includes a fully integrated IEEE 802.3-compliant Ethernet MAC supporting both MII and RMII physical layer interfaces. It operates at 10 or 100 Mbps in full- or half-duplex mode, includes Magic Packet™ wake-on-LAN detection, and complies with IEEE 802.3x flow control. The dedicated EDMAC hardware enables descriptor-based DMA transfers with 2-KB TX/RX FIFOs, minimizing CPU load during network operations.
What are the memory resources available on the R5F563NBCDBG#G0?
The R5F563NBCDBG#G0 integrates 1 Mbyte of on-chip flash memory (executed at 100 MHz with zero wait states), 128 Kbytes of SRAM (also zero-wait), and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles. Flash supports on-board programming via JTAG/FINE and off-board parallel programming (for packages ≥100 pins). The memory map includes 4-Gbyte linear address space with MPU-enforced protection zones.
How does the R5F563NBCDBG#G0 support functional safety standards like IEC60730?
The R5F563NBCDBG#G0 includes multiple hardware features for IEC60730 Class B compliance: oscillation-stop detection for main/sub clocks, dedicated IWDT with independent 125-kHz LOCO clock, CRC calculator with three selectable polynomials, self-diagnostic A/D converter test mode, and memory protection unit (MPU) for runtime code/data isolation. These are documented in Renesas Application Note R01AN1629EU0100 and supported by certified safety libraries.
What is the package type and thermal specification of the R5F563NBCDBG#G0?
The R5F563NBCDBG#G0 is packaged in a 176-ball LFBGA (PLBG0176GA-A) with 13 × 13 mm body size and 0.8-mm ball pitch. It is rated for industrial temperature range of −40 to +105°C (G version), with power supply voltage range of 2.7–3.6 V. Thermal resistance (θJA) is 28°C/W typical; recommended PCB layout includes solid ground plane and thermal vias under the exposed die pad per Renesas Package Outline Drawing L176A-A.
R5F563NBCDBG#G0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX63N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NBCDBG#G0 FAQ
1.How can I place an order for R5F563NBCDBG#G0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NBCDBG#G0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NBCDBG#G0 reliable?
The price and inventory of R5F563NBCDBG#G0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NBCDBG#G0 is usually 5 days.
3.What payment methods are accepted for R5F563NBCDBG#G0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NBCDBG#G0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NBCDBG#G0?
R5F563NBCDBG#G0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NBCDBG#G0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NBCDBG#G0?
For technical support, including R5F563NBCDBG#G0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NBCDBG#G0 requirements.
6.How does Aetrix verify that R5F563NBCDBG#G0 is sourced from the original manufacturer or authorized distributors?
All R5F563NBCDBG#G0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NBCDBG#G0 meets industry standards.
7.What is the process for return or replacement of R5F563NBCDBG#G0?
All R5F563NBCDBG#G0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NBCDBG#G0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NBCDBG#G0 part is unused and in its original packaging.
Return procedure for R5F563NBCDBG#G0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563NBCDBG#G0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

