Renesas R5F563NBCDFC#V0
- Part No.:
- R5F563NBCDFC#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F563NBCDFC#V0.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 176LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563NBCDFC#V0 from Renesas is a 100-MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 1 Mbyte on-chip flash, 128 Kbytes SRAM, and 32 Kbytes data flash. It operates from a 2.7–3.6 V supply, supports -40 to +85°C temperature range, and features 134 general-purpose I/O pins in a 176-pin LQFP package. This MCU targets industrial gateways requiring deterministic real-time control, networked sensing, and secure firmware updates.
For engineers reviewing the R5F563NBCDFC#V0 datasheet, R5F563NBCDFC#V0 pinout, R5F563NBCDFC#V0 application, or R5F563NBCDFC#V0 equivalent, key selection criteria include Ethernet MAC compliance with IEEE 802.3/802.3u (MII/RMII), USB 2.0 full-speed host/function/OTG support, ISO 11898-1 CAN with 32 mailboxes per channel, and AES-128/192/256 encryption via DEU for secure boot and OTA updates.
Technical Context
The R5F563NBCDFC#V0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, supporting 165 DMIPS at 100 MHz and variable-length instructions for ultra-compact code density. Its memory subsystem includes no-wait-state 100-MHz flash access, 128 Kbytes of SRAM usable for instruction/operand storage and deep software standby backup, and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles.
Real-time capability is reinforced by dual timer units: MTU2 (6-channel 16-bit) and TPU (12-channel 16-bit), enabling PWM waveform generation, input capture with digital filtering, phase counting, and A/D conversion trigger synchronization. The device integrates dedicated DMA controllers-DMAC (4 channels), EXDMAC (2 channels), and EDMAC (1 channel for Ethernet)-to offload CPU bandwidth during high-throughput peripheral transfers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK), enabling deterministic real-time execution |
| Flash Memory | 1 Mbyte on-chip main flash, zero wait states at 100 MHz for deterministic boot and ISR latency |
| SRAM | 128 Kbytes on-chip SRAM, no wait states, supports instruction/operand execution and deep software standby backup |
| Ethernet Interface | IEEE 802.3/802.3u-compliant MAC with MII/RMII support, 10/100 Mbps full/half-duplex operation |
| USB Support | Full-speed USB 2.0 host/function/OTG controller with 2 Kbyte on-chip buffer and self-/bus-power mode selection |
| CAN Channels | 3 independent ISO 11898-1 CAN modules, each with 32 mailboxes for robust automotive/industrial messaging |
| Security Engine | Data Encryption Unit (DEU) supporting AES-128/192/256 in ECB/CBC modes for secure firmware and data protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 × 24 mm, 0.5-mm pitch, RoHS-compliant, surface-mount.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual 2.7–3.6 V supply domains (core/analog/USB); 134 I/O pins share common ground reference |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal for precise system clock generation and PLL multiplication |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY register configuration and status monitoring |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII interface signals; RMII mode uses subset (TXD[1:0], RXD[1:0], TX_EN, CRS_DV, REF_CLK) |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) signaling compliant with USB 2.0 specification; internal transceiver eliminates external PHY |
| CAN0_TX / CAN0_RX | Channel 0 CAN transceiver interface | Direct connection to external CAN bus via isolated or non-isolated transceiver; supports standard/extended frames |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | Single-precision IEEE-754 compliant unit enables real-time sensor fusion, motor control algorithms, and signal processing without software emulation overhead |
| Memory Protection Unit (MPU) | Configurable region-based access control prevents unauthorized code/data access, critical for IEC 60730 Class B functional safety compliance |
| Independent Watchdog Timer (IWDT) | Dedicated 14-bit counter driven by 125-kHz LOCO oscillator ensures fail-safe reset even if main clock fails or software hangs |
| Temperature Sensor | On-die ±1°C precision sensor digitized by integrated 12-bit A/D converter, enabling thermal monitoring without external components |
| Parallel Data Capture (PDC) | Direct interface to image sensors or industrial I/O devices; transfers parallel data to RAM/SDRAM via DTC/DMAC without CPU intervention |
| IEBus Interface | Integrated IEBus controller supports half-duplex asynchronous transfer and broadcast communication for automotive body electronics networks |
Applications
| Industrial Ethernet Gateway | Secure PLC Controller |
|---|---|
|
Use Scenario: Edge gateway aggregating Modbus TCP, CANopen, and fieldbus data into unified Ethernet backbone. IC Role / Device Role / Timing Role: Primary MCU executing protocol stacks, managing Ethernet/USB/CAN interfaces, and performing real-time scheduling. Use Value: Integrated Ethernet MAC + 3 CAN channels + USB OTG enable multi-protocol bridging in single-chip solution; 100-MHz FPU accelerates protocol translation and data preprocessing. |
Use Scenario: Programmable logic controller with secure firmware update, runtime diagnostics, and deterministic I/O scanning. IC Role / Device Role / Timing Role: Safety-critical control processor implementing IEC 61131-3 runtimes, CRC validation, and watchdog supervision. Use Value: MPU + IWDT + CRC calculator + DEU AES engine satisfy IEC 60730 Class B requirements; 128 Kbytes SRAM supports large ladder logic execution buffers. |
| Networked Energy Meter | Medical Device Hub |
|
Use Scenario: Smart electricity meter with remote firmware updates, tamper detection, and time-of-use billing over Ethernet/WAN. IC Role / Device Role / Timing Role: Secure metering SoC handling metrology ADC interfacing, RTC-based timestamping, and encrypted communication. Use Value: Built-in RTC with battery backup, 12-bit A/D (21 ch), and AES encryption ensure accurate, auditable, and protected energy data logging. |
Use Scenario: Central hub connecting patient monitors (via USB/RS485), wireless sensors (via CAN), and hospital network (via Ethernet). IC Role / Device Role / Timing Role: Medical-grade communications coordinator managing time-synchronized data acquisition and HIPAA-compliant transmission. Use Value: USB host + CAN + Ethernet + 10-bit D/A (2 ch) enable analog output for legacy medical peripherals; -40 to +85°C rating supports clinical environment reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDFC#V0 | 2 Mbyte flash, 128 Kbytes SRAM, same package and peripheral set | Higher firmware storage capacity for complex protocol stacks or dual-bank OTA updates | Select when >1 Mbyte flash is required for application code, bootloader, and secure storage partitions |
| R5F563NBCDFB#V0 | Same flash/SRAM specs, but 144-pin LQFP (PLQP0144KA-A) package | Reduced I/O count (111 pins vs. 134), no SDRAM interface, fewer timer channels | Choose for cost-sensitive designs where Ethernet + USB + CAN functionality is retained but board space and pin count must be minimized |
Compared with R5F563NBCDFC#V0, R5F563NECDFC#V0 offers double flash capacity for larger embedded applications without changing footprint or peripherals, while R5F563NBCDFB#V0 reduces package size and I/O count at the expense of SDRAM support and peripheral channel count-making it suitable for compact, lower-complexity networked controllers.
Availability
R5F563NBCDFC#V0 is available at Aetrix Electronics and suitable for industrial gateways, programmable logic controllers, smart energy meters, and medical device hubs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563NBCDFC#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The RX63N Group, including R5F563NBCDFC#V0, was designed for deterministic real-time control in networked industrial equipment-integrating Ethernet, USB, CAN, security, and high-precision analog functions in a single chip.
FAQ
What is the maximum operating frequency and core architecture of the R5F563NBCDFC#V0?
The R5F563NBCDFC#V0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with a 5-stage CISC Harvard pipeline. It delivers 165 DMIPS performance and supports single-precision IEEE-754 floating-point operations. The core includes a memory protection unit (MPU), JTAG/FINE debugging interfaces, and variable-length instructions for optimized code density-key for resource-constrained industrial firmware running on R5F563NBCDFC#V0.
Does the R5F563NBCDFC#V0 support Ethernet connectivity, and what standards does it comply with?
Yes, the R5F563NBCDFC#V0 integrates a full IEEE 802.3/802.3u-compliant Ethernet MAC supporting 10/100 Mbps in full- and half-duplex modes. It supports both MII and RMII physical layer interfaces, Magic Packet™ wake-on-LAN, and IEEE 802.3x flow control. The dedicated EDMAC controller handles descriptor-based DMA transfers, reducing CPU load during packet processing-making R5F563NBCDFC#V0 suitable for real-time industrial Ethernet applications.
What are the memory resources available on the R5F563NBCDFC#V0?
The R5F563NBCDFC#V0 includes 1 Mbyte of on-chip flash memory (zero wait states at 100 MHz), 128 Kbytes of SRAM (also zero wait states, usable for instruction/operand execution and deep software standby backup), and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles. These memory resources are directly accessible by the RX core without external glue logic, enabling fast boot times and deterministic interrupt response on R5F563NBCDFC#V0.
How many communication interfaces does the R5F563NBCDFC#V0 support, and which ones are included?
The R5F563NBCDFC#V0 supports Ethernet MAC (1), USB 2.0 full-speed host/function/OTG (2 ports), CAN (3 channels, ISO 11898-1 compliant), SCI (13 channels with UART/SPI/I²C/smart-card modes), I²C (4 channels, up to 1 Mbps), RSPI (3 channels), IEBus (1), and PDC (1). This comprehensive peripheral set allows R5F563NBCDFC#V0 to serve as a central communications hub in multi-protocol industrial systems without external bridge ICs.
Is the R5F563NBCDFC#V0 suitable for functional safety applications, and what features support this?
Yes, the R5F563NBCDFC#V0 includes multiple features aligned with IEC 60730 Class B requirements: oscillation-stoppage detection, hardware CRC calculator, independent watchdog timer (IWDT) with dedicated LOCO clock, self-diagnostic A/D converter function, and memory protection unit (MPU). These capabilities-documented in Renesas' functional safety documentation for the RX63N Group-enable safe runtime monitoring and fault recovery in R5F563NBCDFC#V0-based control systems.
R5F563NBCDFC#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NBCDFC#V0 FAQ
1.How can I place an order for R5F563NBCDFC#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NBCDFC#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NBCDFC#V0 reliable?
The price and inventory of R5F563NBCDFC#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NBCDFC#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NBCDFC#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NBCDFC#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NBCDFC#V0?
R5F563NBCDFC#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NBCDFC#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NBCDFC#V0?
For technical support, including R5F563NBCDFC#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NBCDFC#V0 requirements.
6.How does Aetrix verify that R5F563NBCDFC#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NBCDFC#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NBCDFC#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NBCDFC#V0?
All R5F563NBCDFC#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NBCDFC#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NBCDFC#V0 part is unused and in its original packaging.
Return procedure for R5F563NBCDFC#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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