Renesas R5F563NBDDLC#U0
- Part No.:
- R5F563NBDDLC#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F563NBDDLC#U0.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 177TFLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563NBDDLC#U0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 1 Mbyte on-chip flash, 128 Kbytes SRAM, and 32 Kbytes data flash. It features 133 general-purpose I/O pins (5-V tolerant), hardware AES encryption (DEU), RTC with battery backup, and operates from 2.7–3.6 V at –40 to +85°C. Used in industrial gateways requiring deterministic real-time control and network connectivity.
For engineers reviewing the R5F563NBDDLC#U0 datasheet, R5F563NBDDLC#U0 pinout, R5F563NBDDLC#U0 application, or R5F563NBDDLC#U0 equivalent, this page delivers verified specifications, package mapping to PTLG0177KA-A (177-pin TFLGA), functional context for Ethernet-enabled embedded systems, and validated alternative options for migration or second sourcing.
Technical Context
The R5F563NBDDLC#U0 implements the RXv1 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. It integrates dedicated DMA controllers for Ethernet (EDMAC), USB, and peripheral modules, plus a DTC for event-triggered transfers - all supporting concurrent high-bandwidth operations without CPU intervention.
Its clock system includes PLL-based 100 MHz ICLK, programmable PCLK (up to 50 MHz), and independent oscillators (LOCO, HOCO, subclock) for precise domain partitioning. The MCU supports IEC60730 Class B compliance via built-in CRC calculator, self-diagnostic A/D, oscillation-stop detection, and IWDT with dedicated 125-kHz clock.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC core with 5-stage pipeline, 165 DMIPS @ 100 MHz, IEEE-754 single-precision FPU |
| Memory | 1 Mbyte flash (no wait states @ 100 MHz), 128 Kbytes SRAM (no wait states), 32 Kbytes reprogrammable data flash (100k cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG (full-speed), 3× CAN (ISO 11898-1), 4× I²C (1 Mbps), 13× SCI |
| Analog Peripherals | 21-channel 12-bit A/D (1 µs conversion), 8-channel 10-bit A/D, 2× 10-bit D/A, on-die temperature sensor (±1°C) |
| Timers & Control | MTU2 (6 ch), TPU (12 ch), 4× TMR, 4× CMT, RTC with time-capture, IWDT with dedicated oscillator |
| Security & Compliance | AES-128/192/256 (ECB/CBC) via DEU, CRC calculator (3 polynomials), IEC60730 support functions |
| Package & Environment | PTLG0177KA-A: 177-pin TFLGA, 8 × 8 mm, 0.5-mm pitch, –40 to +85°C operating range (D version) |
Pinout & Package
Package: PTLG0177KA-A - 177-pin Thin Fine-Pitch Land Grid Array (TFLGA), 8 mm × 8 mm, 0.5 mm pitch, 0.7 mm height, lead-free, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual 2.7–3.6 V domains (core/I/O); 13 dedicated VCC/VSS pairs ensure low-noise operation across high-speed peripherals |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3u-compliant MDIO bus for PHY register access and configuration; supports auto-negotiation and link status monitoring |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII interface signals; full 4-bit parallel path enables 100 Mbps baseband transfer with synchronous clocking (ETH_TX_CLK/ETH_RX_CLK) |
| USB_VBUS / USB_ID / USB_DP / USB_DM | USB 2.0 physical layer | Full-speed OTG-capable interface; VBUS sensing enables host/peripheral role switching; ID pin detects cable orientation for OTG negotiation |
| AD00–AD20 / AD0–AD7 | Analog input channels | 21× 12-bit and 8× 10-bit A/D inputs with shared sample-and-hold; selectable reference (VREFH/VSS) and software/triggered start modes |
| DA0 / DA1 | Digital-to-analog outputs | 2× 10-bit buffered voltage outputs (0–VREFH); independent update control supports synchronized waveform generation |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Dedicated 2 KB TX/RX FIFO and descriptor-based DMA offloads TCP/IP stack processing, reducing CPU load by >40% in packet-forwarding tasks |
| IEC60730 Class B Support | Integrated CRC calculator, A/D self-test, clock failure detection, and IWDT enable certified safety firmware execution without external watchdog supervision |
| Hardware AES Engine (DEU) | Zero-cycle-overhead encryption/decryption for TLS handshake acceleration and secure firmware updates; supports ECB/CBC with key lengths up to 256 bits |
| Flexible Clock Architecture | Independent ICLK/PCLK/FCLK/BCLK domains allow simultaneous 100 MHz CPU, 50 MHz peripherals, 50 MHz FlashIF, and 50 MHz external bus operation |
| RTC with Time-Capture | Three timestamp registers capture exact event timing on external pins (e.g., pulse edges), enabling precise synchronization in motion control or power metering |
Applications
| Industrial Ethernet Gateway | Smart Energy Meter |
|---|---|
|
Use Scenario: Aggregates Modbus RTU/TCP data from field devices and bridges to cloud via MQTT over Ethernet. IC Role / Device Role / Timing Role: Primary controller executing protocol translation, real-time scheduling, and secure TLS communication. Use Value: Integrated Ethernet MAC + FPU enables deterministic packet handling and floating-point energy calculations without external co-processors. |
Use Scenario: Measures active/reactive power, harmonics, and tamper events in DIN-rail mounted utility meters. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC sampling, RTC-based billing intervals, and secure firmware updates. Use Value: On-chip 12-bit A/D with sample-and-hold and hardware CRC ensures metrology accuracy and data integrity per IEC62053. |
| Programmable Logic Controller (PLC) Base Unit | Building Automation Controller |
|
Use Scenario: Executes ladder logic and motion control algorithms while communicating with HMI and remote I/O over EtherCAT or custom Ethernet protocols. IC Role / Device Role / Timing Role: Real-time deterministic controller with MTU2/TPU PWM outputs and Ethernet-triggered interrupt latency < 200 ns. Use Value: 133 GPIOs (5-V tolerant) support direct connection to industrial sensors/actuators; hardware AES secures firmware updates against unauthorized modification. |
Use Scenario: Manages HVAC, lighting, and access control subsystems in commercial buildings using BACnet/IP and KNX over Ethernet. IC Role / Device Role / Timing Role: Network-aware application processor running embedded Linux or bare-metal RTOS with deterministic Ethernet response. Use Value: Dual USB ports (host/function) simplify field service via USB flash drives or debug interfaces; RTC with battery backup maintains schedule during AC loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDLC#U0 | 2 Mbyte flash, same 128 Kbyte SRAM, identical package and peripheral set | Supports larger firmware images (e.g., dual-bank OTA, extended protocol stacks) | Select when firmware size exceeds 1 Mbyte or future scalability is required; pin-compatible with no layout change |
| R5F563NBDDFC#U0 | LQFP-176 (PLQP0176KB-A), same 1 Mbyte flash/SRAM, but lacks Ethernet MAC and PDC | Suitable for non-networked control applications where cost and PCB assembly simplicity are prioritized | Choose for cost-sensitive designs without Ethernet; requires board redesign due to different package and missing ETH pins |
Compared with R5F563NBDDLC#U0, R5F563NECDLC#U0 offers double flash capacity for complex protocol stacks, while R5F563NBDDFC#U0 trades Ethernet capability for lower unit cost and LQFP manufacturability - neither is pin-compatible except within same package family.
Availability
R5F563NBDDLC#U0 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, PLC base units, and building automation controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563NBDDLC#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX63N Group, including R5F563NBDDLC#U0, was designed for Ethernet-connected industrial control applications demanding real-time determinism, functional safety support, and cryptographic security in compact form factors.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563NBDDLC#U0?
The R5F563NBDDLC#U0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance. Its RXv1 32-bit CPU core includes a single-precision IEEE-754 floating-point unit, enabling efficient execution of control algorithms and signal processing tasks without external math coprocessors. This performance level is sustained across its full operating temperature range of –40 to +85°C.
Does the R5F563NBDDLC#U0 include an Ethernet controller, and what interface standards does it support?
Yes, the R5F563NBDDLC#U0 includes a fully integrated Ethernet MAC supporting both 10 and 100 Mbps operation in full- and half-duplex modes. It complies with IEEE 802.3 and supports MII and RMII physical layer interfaces, flow control per IEEE 802.3x, and Magic Packet™ wake-on-LAN functionality - making it suitable for industrial Ethernet applications without requiring external PHY or MAC logic.
What memory resources are available on the R5F563NBDDLC#U0?
The R5F563NBDDLC#U0 integrates 1 Mbyte of on-chip flash memory (with zero wait states at 100 MHz), 128 Kbytes of SRAM (also zero wait states), and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles. These resources support robust firmware storage, real-time data buffering, and non-volatile parameter retention - all accessible via the MCU's unified 4-Gbyte linear address space.
How does the R5F563NBDDLC#U0 support functional safety standards like IEC60730?
The R5F563NBDDLC#U0 includes hardware features essential for IEC60730 Class B compliance: a CRC calculator with three configurable polynomials, self-diagnostic capability for the 10-bit A/D converter, oscillation-stoppage detection for main/subclocks, and an independent watchdog timer (IWDT) driven by a dedicated 125-kHz on-chip oscillator. These enable runtime verification of memory, clocks, and analog subsystems without software overhead.
What package type and pin count does the R5F563NBDDLC#U0 use?
The R5F563NBDDLC#U0 is packaged in the PTLG0177KA-A - a 177-pin Thin Fine-Pitch Land Grid Array measuring 8 mm × 8 mm with 0.5 mm pitch. This package provides 133 general-purpose I/O pins (5-V tolerant), dedicated Ethernet and USB signal routing, and thermal performance suited for industrial environments. It is RoHS compliant and lead-free.
R5F563NBDDLC#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NBDDLC#U0 FAQ
1.How can I place an order for R5F563NBDDLC#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NBDDLC#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NBDDLC#U0 reliable?
The price and inventory of R5F563NBDDLC#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NBDDLC#U0 is usually 5 days.
3.What payment methods are accepted for R5F563NBDDLC#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NBDDLC#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NBDDLC#U0?
R5F563NBDDLC#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NBDDLC#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NBDDLC#U0?
For technical support, including R5F563NBDDLC#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NBDDLC#U0 requirements.
6.How does Aetrix verify that R5F563NBDDLC#U0 is sourced from the original manufacturer or authorized distributors?
All R5F563NBDDLC#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NBDDLC#U0 meets industry standards.
7.What is the process for return or replacement of R5F563NBDDLC#U0?
All R5F563NBDDLC#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NBDDLC#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NBDDLC#U0 part is unused and in its original packaging.
Return procedure for R5F563NBDDLC#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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