Renesas R5F563NBDDLK#U0
- Part No.:
- R5F563NBDDLK#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F563NBDDLK#U0.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,508
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Product details
Overview
R5F563NBDDLK#U0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision FPU, 1 Mbyte on-chip flash, 128 Kbytes SRAM, and 32 Kbytes data flash. It features 12-bit and 10-bit A/D converters (21 + 8 channels), dual 10-bit D/A outputs, CAN v2.0B (3 channels), USB 2.0 host/function/OTG, and operates from 2.7–3.6 V in industrial temperature range (−40 to +85°C). It targets networked industrial controllers requiring deterministic real-time control and secure connectivity.
For engineers reviewing the R5F563NBDDLK#U0 datasheet, R5F563NBDDLK#U0 pinout, R5F563NBDDLK#U0 application, or R5F563NBDDLK#U0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 176-pin LFBGA package compatibility, 100-MHz timing margin for deterministic ISR latency, and DEU-based AES-128/192/256 encryption for IEC 60730 Class B compliance in safety-critical firmware updates.
Technical Context
The R5F563NBDDLK#U0 implements the 32-bit RX CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling 165 DMIPS at 100 MHz. It integrates dedicated hardware accelerators including a 32×32→64-bit multiplier (1-cycle), divider (2-cycle), and IEEE-754-compliant FPU for real-time signal processing.
Its peripheral subsystem includes an Ethernet controller (ETHERC) with 2-Kbyte TX/RX FIFOs and descriptor-based EDMAC, three CAN modules (32 mailboxes each), and a parallel data capture unit (PDC) supporting image sensor interfacing via DTC/DMAC-designed for embedded vision edge nodes with low-latency frame ingestion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RX 32-bit CISC CPU with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Clock | 100 MHz system clock (ICLK); supports 50 MHz PCLK/FCLK/BCLK for peripherals and external bus |
| Memory | 1 Mbyte flash (no wait states @ 100 MHz), 128 Kbytes SRAM (no wait states), 32 Kbytes reprogrammable data flash (100k cycles) |
| Analog | 21-channel 12-bit A/D (1 μs conversion @ 50 MHz PCLK), 8-channel 10-bit A/D, 2-channel 10-bit D/A, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG (full-speed), 3× CAN, 13× SCI, 4× RIIC (1 Mbps), 3× RSPI |
| Security & Safety | Data Encryption Unit (AES-128/192/256, ECB/CBC), CRC calculator (3 polynomials), MPU, oscillation-stop detection, IWDT |
| Package | PTLG0145KA-A: 145-pin TFLGA, 7 mm × 7 mm, 0.5 mm pitch, 5-V-tolerant I/O (18 pins) |
Pinout & Package
Package: PTLG0145KA-A - 145-pin Thin Fine-Pitch Land Grid Array (TFLGA), 7 mm × 7 mm body, 0.5 mm pitch, 0.7 mm height, lead-free, RoHS compliant. Designed for high-density PCB layouts with thermal pad under die for enhanced heat dissipation in fanless industrial enclosures.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | 12 dedicated VCC/VSS pairs for analog/digital domain separation; decoupling required per Renesas layout guidelines |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables PLL lock for 100 MHz ICLK generation |
| MD[3:0] | Mode selection inputs | Configure boot mode (ROM/flash), debug interface (JTAG/FINE), and reset vector source at power-on |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC for PHY register access and link status polling |
| USB_VBUS / USB_ID | USB OTG role detection | Enables automatic host/device role switching; USB_ID pin selects OTG function during enumeration |
| AD00–AD20 | Analog input channels | 21 dedicated pins for 12-bit A/D; shared with GPIO but require analog input buffer enable and reference voltage (VREFH/VREFL) |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Hardware-accelerated packet handling with 2-Kbyte TX/RX FIFOs and descriptor DMA reduces CPU load to <5% during 100 Mbps line-rate traffic |
| USB 2.0 Host/Function/OTG | Single-port dual-role controller with 2-Kbyte on-chip RAM buffer; supports CDC, HID, and MSC class drivers without external memory |
| Real-time Timer System | MTU2 (6-channel), TPU (12-channel), CMT (4-channel), and RTC with battery backup enable sub-microsecond PWM, encoder counting, and calendar-aware scheduling |
| IEC 60730 Support | Integrated self-test functions: oscillation-stop detection, CRC engine, IWDT, A/D converter diagnostic, and memory protection unit (MPU) for Class B compliance |
| Data Encryption Unit (DEU) | AES-128/192/256 encryption/decryption in ECB/CBC modes with zero-CPU-overhead operation; key storage isolated from general memory space |
Applications
| Industrial PLC Controller | Building Automation Gateway |
|---|---|
Use Scenario: Standalone DIN-rail-mounted controller managing HVAC actuators, lighting zones, and occupancy sensors over BACnet/IP and Modbus TCP. IC Role / Device Role / Timing Role: Primary real-time execution engine with Ethernet MAC for IP stack offload, CAN for legacy fieldbus bridging, and 12-bit A/D for analog sensor conditioning. Use Value: Integrated 100-MHz RX core and hardware CRC/DEU enable deterministic 10-ms control loop execution while signing firmware updates per IEC 62443-3-3. |
Use Scenario: Edge gateway aggregating KNX, DALI, and Zigbee devices into a unified MQTT broker with TLS-secured cloud uplink. IC Role / Device Role / Timing Role: Dual-role USB host (for Zigbee dongle) and function (for configuration via PC), plus Ethernet MAC for LAN-side TLS termination. Use Value: On-chip 256-Kbyte SRAM variant not required-128 Kbytes suffices for concurrent TCP/IP stack, USB device stack, and lightweight TLS handshake with hardware AES acceleration. |
| Medical Infusion Pump | Smart Energy Meter |
Use Scenario: UL 60601-1-certified infusion pump with flow rate control, occlusion detection, and wireless telemetry via Wi-Fi module (connected via SPI/UART). IC Role / Device Role / Timing Role: Safety-critical controller executing FDA-required watchdog supervision, motor PWM (MTU2), pressure sensor A/D sampling, and encrypted log storage. Use Value: Independent watchdog timer (IWDT) with dedicated LOCO clock ensures fail-safe shutdown even if main PLL fails; DEU secures audit logs against tampering. |
Use Scenario: ANSI C12.22-compliant smart meter with HAN (Home Area Network) interface, pulse output for mechanical metering, and RF mesh backhaul. IC Role / Device Role / Timing Role: Time-synchronized data concentrator using RTC with leap-year compensation and 10-bit D/A for analog pulse generation. Use Value: Hardware RTC with battery backup maintains accurate billing timestamps across power outages; 145-pin TFLGA enables compact 2-layer PCB design for cost-sensitive meter housings. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDLK#U0 | 2 Mbyte flash (vs. 1 Mbyte), same 128 Kbytes SRAM, identical package and peripheral set | Required when firmware image exceeds 1 Mbyte (e.g., dual-bank OTA with full crypto stack + web server) | Select R5F563NEDDLK#U0 only if flash headroom >512 Kbytes is needed; otherwise R5F563NBDDLK#U0 optimizes BoM cost |
| R5F563NBCDLK#U0 | Same 1 Mbyte flash, 128 Kbytes SRAM, but 145-pin TFLGA package with reduced I/O count (111 GPIO vs. 133 in larger packages) | Suitable for cost-constrained designs where full I/O expansion is unnecessary (e.g., fixed-function gateways) | R5F563NBCDLK#U0 shares identical core/peripheral specs but lacks PDC and some SCI channels-verify peripheral mapping before substitution |
Compared with R5F563NBDDLK#U0, R5F563NEDDLK#U0 provides double flash capacity for complex protocol stacks, while R5F563NBCDLK#U0 trades I/O count for lower unit cost-neither is pin-compatible, but all three share identical clock, power, and debug interface footprints.
Availability
R5F563NBDDLK#U0 is available at Aetrix Electronics and suitable for industrial automation, building management systems, and medical device applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized Renesas distribution channels.
Supply support for R5F563NBDDLK#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets, with deep expertise in real-time embedded systems.
The RX63N Group, including R5F563NBDDLK#U0, was engineered for deterministic industrial control with integrated Ethernet, functional safety features (IEC 60730), and hardware security-targeting programmable logic controllers, HMIs, and networked medical equipment.
FAQ
What is the maximum operating frequency and core performance of the R5F563NBDDLK#U0?
The R5F563NBDDLK#U0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using the 32-bit RX CPU core. Its 5-stage pipeline, variable-length instruction set, and single-cycle 32×32 multiplier enable deterministic real-time execution. The R5F563NBDDLK#U0 achieves this performance while maintaining low power consumption (500 μA/MHz) and full peripheral integration-including Ethernet MAC, USB, and CAN-making it suitable for time-critical industrial control tasks.
Does the R5F563NBDDLK#U0 support Ethernet connectivity, and what interfaces are available?
Yes, the R5F563NBDDLK#U0 includes a fully integrated Ethernet MAC (ETHERC) compliant with IEEE 802.3, supporting 10/100 Mbps in full- and half-duplex modes. It supports both MII and RMII physical layer interfaces, Magic Packet™ wake-on-LAN, and IEEE 802.3x flow control. The dedicated EDMAC handles descriptor-based packet transfers, offloading the CPU and enabling efficient TCP/IP stack implementation in the R5F563NBDDLK#U0's 128 Kbytes of SRAM.
What are the memory resources available on the R5F563NBDDLK#U0?
The R5F563NBDDLK#U0 integrates 1 Mbyte of on-chip flash memory (executed at 100 MHz with zero wait states), 128 Kbytes of SRAM (also zero-wait), and 32 Kbytes of reprogrammable data flash rated for 100,000 erase/write cycles. This memory configuration supports robust firmware partitioning-e.g., separate secure boot loader, application code, and encrypted parameter storage-all within the R5F563NBDDLK#U0 without external memory components.
How does the R5F563NBDDLK#U0 support functional safety standards like IEC 60730?
The R5F563NBDDLK#U0 includes multiple hardware features for IEC 60730 Class B compliance: oscillation-stop detection for clock monitoring, independent watchdog timer (IWDT) with dedicated LOCO clock, CRC calculator with three selectable polynomials, self-diagnostic A/D converter test, and memory protection unit (MPU). These capabilities are documented in Renesas' safety manual for the RX63N Group and are directly implemented in the R5F563NBDDLK#U0 silicon-enabling certified firmware development without external safety monitors.
What package type and pin count does the R5F563NBDDLK#U0 use?
The R5F563NBDDLK#U0 uses the PTLG0145KA-A package: a 145-pin Thin Fine-Pitch Land Grid Array measuring 7 mm × 7 mm with 0.5 mm pitch. It provides 111 general-purpose I/O pins (including 18 with 5-V tolerance), dedicated Ethernet and USB signals, and a thermal pad for thermal management. This package balances high peripheral density with compact footprint-ideal for space-constrained industrial and medical PCBs where the R5F563NBDDLK#U0 serves as the central controller.
R5F563NBDDLK#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NBDDLK#U0 FAQ
1.How can I place an order for R5F563NBDDLK#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NBDDLK#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NBDDLK#U0 reliable?
The price and inventory of R5F563NBDDLK#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NBDDLK#U0 is usually 5 days.
3.What payment methods are accepted for R5F563NBDDLK#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NBDDLK#U0 transactions.
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R5F563NBDDLK#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NBDDLK#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NBDDLK#U0?
For technical support, including R5F563NBDDLK#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NBDDLK#U0 requirements.
6.How does Aetrix verify that R5F563NBDDLK#U0 is sourced from the original manufacturer or authorized distributors?
All R5F563NBDDLK#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NBDDLK#U0 meets industry standards.
7.What is the process for return or replacement of R5F563NBDDLK#U0?
All R5F563NBDDLK#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NBDDLK#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NBDDLK#U0 part is unused and in its original packaging.
Return procedure for R5F563NBDDLK#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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