Renesas R5F563NDCDBG#G0
- Part No.:
- R5F563NDCDBG#G0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F563NDCDBG#G0.pdf
- Description:
- RX63N 1.5MB/128KB BGA176 100MHZ
- Quantity:
- Payment:

- Shipping:

Inventory:1,133
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Product details
Overview
R5F563NDCDBG#G0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 1.5 MB on-chip flash, 128 KB SRAM, and 32 KB data flash. It features 134 general-purpose I/O pins (5-V tolerant), hardware AES encryption (DEU), and operates from 2.7–3.6 V across –40 to +85°C. Used in industrial gateways requiring deterministic real-time control, networked HMI, and secure firmware updates.
For engineers reviewing the R5F563NDCDBG#G0 datasheet, R5F563NDCDBG#G0 pinout, R5F563NDCDBG#G0 application, or R5F563NDCDBG#G0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 100-MHz deterministic timing, integrated DEU for secure boot, and compatibility with Renesas E20/E1 debug interfaces - all confirmed for this LFBGA176 package variant.
Technical Context
The R5F563NDCDBG#G0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, supporting 165 DMIPS at 100 MHz and IEEE-754 single-precision floating-point operations. Its memory subsystem includes zero-wait-state 100-MHz flash and SRAM, plus dedicated EDMAC for Ethernet DMA offloading.
It integrates dual-clock domain operation: ICLK up to 100 MHz for CPU/core logic, PCLK up to 50 MHz for peripherals, and independent BCLK/SDRAM clocks. Real-time capabilities are reinforced by MTU2 (6-channel 16-bit timer), TPU (12-channel), RTC with battery backup, and four low-power modes including deep software standby with SRAM retention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RX 32-bit CPU, 100 MHz max - delivers 165 DMIPS with deterministic interrupt latency and MPU-enforced memory protection. |
| Memory | 1.5 MB flash (no wait states @100 MHz), 128 KB SRAM (no wait states), 32 KB reprogrammable data flash - enables field firmware updates without external storage. |
| Ethernet Interface | IEEE 802.3-compliant MAC with MII/RMII support, 10/100 Mbps full/half-duplex - eliminates need for external PHY in cost-sensitive industrial Ethernet nodes. |
| Analog Peripherals | 21-channel 12-bit ADC (1 µs conversion @50 MHz PCLK), 8-channel 10-bit ADC, 2×10-bit DAC, on-die temperature sensor (±1°C) - supports closed-loop motor control and sensor fusion. |
| Security & Crypto | Data Encryption Unit (DEU) with AES-128/192/256 in ECB/CBC mode - enables secure boot, encrypted OTA updates, and IP protection without external crypto IC. |
| Package & Temp | LFBGA176 (PLBG0176GA-A, 13×13 mm, 0.8-mm pitch), industrial temp range (–40 to +85°C) - suitable for high-density PCB layouts in harsh environments. |
| Debug & Programming | JTAG and FINE two-wire interfaces, on-chip ROM-less boot capability - simplifies production programming and field debugging with Renesas E20 emulator. |
Pinout & Package
Package: PLBG0176GA-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 13 × 13 mm body, 0.8 mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated power domains for core (VCC), analog (AVCC0), USB (VCC_USB), and backup (VBATT) - enables noise isolation and battery-backed RTC operation. |
| MDIO / MDC | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC signals for PHY configuration - allows dynamic link negotiation and status monitoring without CPU overhead. |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet transmit/receive data | MII-mode 4-bit parallel data lanes - supports 100 Mbps full-duplex transfer with minimal external component count. |
| ETX_EN / ETX_CLK / ERX_DV / ERX_CLK | Ethernet control & clock | Synchronous handshaking signals for MII - ensures precise timing alignment between MCU and PHY for error-free frame transmission. |
| USB_DP / USB_DM | Full-speed USB 2.0 differential pair | Integrated transceiver compliant with USB 2.0 FS (12 Mbps) - supports host/function/OTG roles without external PHY or level shifters. |
| MTU2A0–MTU2A5 | Multi-function timer waveform outputs | 6-channel complementary PWM outputs with dead-time insertion - directly drives 3-phase inverter stages in motor control applications. |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Hardware-accelerated descriptor-based DMA engine reduces CPU load by >70% during sustained 100 Mbps packet throughput. |
| Floating-Point Unit (FPU) | IEEE-754 single-precision execution in one cycle per operation - accelerates real-time filtering, PID computation, and sensor math without software emulation. |
| Programmable Pulse Generator (PPG) | 32-channel pulse output triggered by MTU2/TPU events - enables precise timing of external peripherals (e.g., LED drivers, stepper controllers) with sub-microsecond jitter. |
| IEBus & CAN Interfaces | 1× IEBus (automotive infotainment bus) + 3× ISO 11898-1 CAN channels (32 mailboxes each) - supports mixed-protocol vehicle gateway designs. |
| Temperature Sensor + 12-bit ADC | On-die ±1°C sensor digitized via dedicated A/D channel - provides real-time thermal monitoring for fan control and overtemperature shutdown without external components. |
| Unique ID (G version) | 16-byte factory-programmed device identifier - enables secure device authentication and cryptographic key binding in IoT edge deployments. |
Applications
| Industrial Ethernet Gateway | Secure HMI Controller |
|---|---|
Use Scenario: Protocol translation between Modbus TCP, EtherNet/IP, and fieldbus networks in factory automation. IC Role / Device Role / Timing Role: Primary application processor with integrated Ethernet MAC, dual CAN, and real-time OS scheduling. Use Value: Eliminates external Ethernet PHY and protocol offload ICs, reducing BOM cost by ~$1.80 and PCB area by 22 mm². |
Use Scenario: Touch-enabled operator interface with encrypted firmware updates and tamper-resistant boot. IC Role / Device Role / Timing Role: Secure application host managing display, touch, USB OTG, and AES-encrypted OTA update verification. Use Value: On-chip DEU and unique ID enable FIPS-compliant secure boot and device identity binding - no external TPM required. |
| Networked Motor Drive | Smart Energy Meter |
Use Scenario: Closed-loop servo control with real-time Ethernet feedback and thermal protection. IC Role / Device Role / Timing Role: Real-time controller executing 20 kHz PWM generation (MTU2), current sensing (12-bit ADC), and temperature monitoring. Use Value: Integrated 100-MHz MTU2 and 12-bit ADC with sample-and-hold achieve <500 ns PWM jitter and 1 µs conversion - meets IEC 61800-3 Class A EMC requirements. |
Use Scenario: Revenue-grade metering with time-of-use billing, remote firmware updates, and anti-tampering detection. IC Role / Device Role / Timing Role: Metering SoC handling metrology (ADC), RTC calendar, secure communication (AES), and HPLC/RF mesh networking. Use Value: Battery-backed RTC with alarm interrupts and CRC calculator enable accurate timestamping and integrity checking of energy logs - certified for ANSI C12.22 compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDBG#G0 | 2 MB flash, same 128 KB SRAM, identical LFBGA176 package and peripheral set - differs only in flash capacity. | Required where firmware image size exceeds 1.5 MB (e.g., dual-bank OTA with full feature set). | Select R5F563NECDBG#G0 when future firmware growth or safety-certified redundancy mandates >1.5 MB code space. |
| R5F563NDCDFC#G0 | LQFP176 package (PLQP0176KB-A), same 1.5 MB flash/SRAM/peripherals - differs in package type, thermal performance, and board assembly process. | Preferred for prototyping, manual soldering, or legacy PCBs designed for QFP footprints. | Choose R5F563NDCDFC#G0 for design flexibility in non-high-density layouts or where LFBGA rework is not supported. |
Compared with R5F563NDCDBG#G0, the R5F563NECDBG#G0 offers headroom for larger firmware images without changing layout, while R5F563NDCDFC#G0 trades LFBGA density for LQFP manufacturability - both retain identical real-time, security, and connectivity capabilities.
Availability
R5F563NDCDBG#G0 is available at Aetrix Electronics and suitable for industrial gateways, secure HMIs, networked motor drives, and smart energy meters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F563NDCDBG#G0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX63N Group is engineered for deterministic real-time control in networked industrial systems, integrating Ethernet, USB, CAN, and hardware security to reduce system-level complexity and certification effort.
FAQ
What is the maximum operating frequency and core architecture of the R5F563NDCDBG#G0?
The R5F563NDCDBG#G0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with a 5-stage CISC Harvard pipeline. It achieves 165 DMIPS and includes a single-precision IEEE-754 floating-point unit, memory protection unit (MPU), and JTAG/FINE debug interfaces - all confirmed in the official Renesas R01DS0098EJ0180 datasheet for the R5F563NDCDBG#G0.
Does the R5F563NDCDBG#G0 support Ethernet connectivity, and what interface options are available?
Yes, the R5F563NDCDBG#G0 integrates a full IEEE 802.3-compliant Ethernet MAC supporting both MII and RMII physical layer interfaces at 10/100 Mbps. It includes dedicated EDMAC hardware for descriptor-based DMA, 2 KB TX/RX FIFOs, and Magic Packet™ wake-on-LAN - all documented for the R5F563NDCDBG#G0 in the RX63N Group datasheet Rev.1.80.
What are the memory resources available on the R5F563NDCDBG#G0?
The R5F563NDCDBG#G0 includes 1.5 MB of on-chip flash memory (zero wait states at 100 MHz), 128 KB of SRAM (zero wait states), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These values are explicitly specified for the R5F563NDCDBG#G0 in Table 1.3 of the Renesas R01DS0098EJ0180 datasheet under the RX63N D-version product list.
Is hardware cryptographic acceleration available on the R5F563NDCDBG#G0?
Yes, the R5F563NDCDBG#G0 incorporates a Data Encryption Unit (DEU) supporting AES-128/192/256 encryption and decryption in ECB and CBC modes. This hardware accelerator is confirmed for the R5F563NDCDBG#G0 in the "Features" section of the RX63N Group datasheet (R01DS0098EJ0180), enabling secure boot and OTA firmware updates without software overhead.
What package type and pin count does the R5F563NDCDBG#G0 use?
The R5F563NDCDBG#G0 uses the PLBG0176GA-A package: a 176-ball Low-Profile Fine-Pitch Ball Grid Array with 13 × 13 mm body size and 0.8 mm ball pitch. This package is explicitly assigned to the R5F563NDCDBG#G0 in Table 1.3 of the Renesas R01DS0098EJ0180 datasheet and supports all its I/O and thermal specifications for industrial operation.
R5F563NDCDBG#G0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX63N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NDCDBG#G0 FAQ
1.How can I place an order for R5F563NDCDBG#G0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NDCDBG#G0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NDCDBG#G0 reliable?
The price and inventory of R5F563NDCDBG#G0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NDCDBG#G0 is usually 5 days.
3.What payment methods are accepted for R5F563NDCDBG#G0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NDCDBG#G0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NDCDBG#G0?
R5F563NDCDBG#G0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NDCDBG#G0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NDCDBG#G0?
For technical support, including R5F563NDCDBG#G0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NDCDBG#G0 requirements.
6.How does Aetrix verify that R5F563NDCDBG#G0 is sourced from the original manufacturer or authorized distributors?
All R5F563NDCDBG#G0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NDCDBG#G0 meets industry standards.
7.What is the process for return or replacement of R5F563NDCDBG#G0?
All R5F563NDCDBG#G0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NDCDBG#G0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NDCDBG#G0 part is unused and in its original packaging.
Return procedure for R5F563NDCDBG#G0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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