Renesas R5F563NDCDFB#V0
- Part No.:
- R5F563NDCDFB#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F563NDCDFB#V0.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,651
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Product details
Overview
R5F563NDCDFB#V0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 1.5 Mbytes on-chip flash, 128 Kbytes SRAM, and 32 Kbytes data flash. It features 144-pin LQFP (PLQP0144KA-A) packaging, operates from 2.7–3.6 V, supports -40 to +85°C industrial temperature range, and integrates USB 2.0 host/function/OTG, CAN, and 12-bit A/D converters. It is designed for networked industrial control and gateway applications requiring deterministic real-time response and secure communications.
For engineers reviewing the R5F563NDCDFB#V0 datasheet, R5F563NDCDFB#V0 pinout, R5F563NDCDFB#V0 application, or R5F563NDCDFB#V0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 100 MHz CPU performance (165 DMIPS), integrated DEU AES encryption, RTC with battery backup, and IEC60730 safety compliance features including CRC, self-diagnostic A/D, and oscillation-stop detection.
Technical Context
The R5F563NDCDFB#V0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, variable-length instructions, and memory protection unit (MPU). It executes at up to 100 MHz with 165 DMIPS and includes dedicated hardware for single-precision floating-point arithmetic per IEEE-754.
Its peripheral set is optimized for connectivity: integrated Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG controller with 2 Kbytes buffer, three CAN channels (ISO11898-1 compliant, 32 mailboxes each), and four I²C interfaces (one FM+ capable, up to 1 Mbps). The device supports deterministic real-time operation via 20+ timers including MTU2, TPU, and CMT modules with trigger synchronization to A/D conversion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RX 32-bit CPU, 100 MHz max, 165 DMIPS, IEEE-754 FPU, 5-stage pipeline |
| Memory | 1.5 Mbytes flash (no wait states @100 MHz), 128 Kbytes SRAM, 32 Kbytes reprogrammable data flash (100k cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG, 3× CAN, 13× SCI, 4× I²C, 3× RSPI |
| Analog | 21-channel 12-bit A/D (1 µs conversion @50 MHz PCLK), 8-channel 10-bit A/D, 2× 10-bit D/A, on-die temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256 encryption/decryption (ECB/CBC), CRC calculator, IEC60730-compliant self-diagnostic A/D, oscillation-stop detection |
| Power & Temp | 2.7–3.6 V supply, -40 to +85°C operating range, four low-power modes (deep software standby with SRAM retention) |
| Package | 144-pin LQFP (PLQP0144KA-A), 20 × 20 mm, 0.5 mm pitch, 111 general-purpose I/O pins (18× 5-V tolerant) |
Pinout & Package
Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch, exposed pad (thermal pad not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated power/ground pairs per I/O bank; decoupling required per Renesas layout guidelines |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables PLL-based 100 MHz system clock |
| MD0 / MD1 | Mode selection inputs | Configure boot mode (single-chip, ROM-enabled/disabled expansion) at reset |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC for PHY register access and configuration |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data bus | MII interface signals; RMII mode uses subset (TXD[1:0], RXD[1:0], TX_EN, CRS_DV, REF_CLK) |
| USB_VBUS / USB_ID / USB_DP / USB_DM | USB 2.0 physical layer | Full-speed (12 Mbps) OTG-capable interface; VBUS sensing and ID pin enable host/peripheral role negotiation |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC with EDMAC | Dedicated 2 Kbyte Tx/Rx FIFO and descriptor-based DMA offloads CPU during frame processing |
| USB 2.0 Host/Function/OTG | Single-port dual-role controller with integrated transceiver and 2 Kbyte RAM buffer enables embedded host peripherals or device enumeration |
| IEC60730 Safety Support | Hardware-accelerated CRC, IWDT with dedicated LOCO clock, A/D self-test, and clock failure detection meet Class B requirements |
| Flexible Clock System | Multiple independent clocks (ICLK, PCLK, FCLK, BCLK) allow dynamic frequency scaling per subsystem without compromising timing integrity |
| Real-Time Timer Suite | MTU2 (6-channel), TPU (12-channel), CMT (4-channel), and RTC with time-capture enable precise event synchronization and PWM generation |
Applications
| Industrial Ethernet Gateway | Secure PLC Communication Module |
|---|---|
Use Scenario: Aggregating Modbus TCP, EtherNet/IP, or PROFINET fieldbus data across legacy RS-485 networks into a unified Ethernet backbone. IC Role / Device Role / Timing Role: Primary application processor executing protocol stacks, managing dual Ethernet ports (MAC + external PHY), and synchronizing real-time I/O via MTU2-triggered A/D sampling. Use Value: Integrated Ethernet MAC and USB OTG eliminate external PHY and bridge ICs; 100 MHz FPU accelerates floating-point control algorithms; DEU enables encrypted firmware updates over-the-air. |
Use Scenario: Embedded communication module in programmable logic controllers handling secure remote diagnostics, firmware updates, and HMI data exchange. IC Role / Device Role / Timing Role: Safety-certified controller running IEC60730-compliant runtime checks while managing CANopen and USB CDC ACM virtual COM port simultaneously. Use Value: Hardware CRC, self-diagnostic A/D, and oscillation-stop detection satisfy Class B functional safety; 32 Kbytes data flash stores encrypted keys and audit logs; RTC with battery backup maintains timestamp integrity during power loss. |
| Networked Building Automation Controller | Medical Device Connectivity Hub |
Use Scenario: HVAC, lighting, and access control integration node communicating via BACnet/IP and LonWorks over managed Ethernet switches. IC Role / Device Role / Timing Role: Real-time scheduler coordinating 12-bit A/D readings from temperature/humidity sensors, PWM fan control via MTU2, and packetized Ethernet transmission using EDMAC descriptors. Use Value: 144-pin LQFP provides ample I/O for multi-sensor interfacing; 128 Kbytes SRAM buffers large BACnet MSTP frames; low-power modes extend uptime in battery-backed installations. |
Use Scenario: Secure data concentrator aggregating ECG, SpO₂, and NIBP measurements from bedside monitors and transmitting HIPAA-compliant payloads to hospital EMR systems. IC Role / Device Role / Timing Role: Trusted execution environment performing AES-256 encryption of sensor data prior to USB mass storage or Ethernet transmission; temperature sensor validates thermal derating during high-duty-cycle operation. Use Value: On-chip DEU eliminates external crypto co-processor; medical-grade ±1°C temperature sensor enables real-time thermal compensation of analog front-end; IEC60730 features support FDA Class II device certification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDFB#V0 | 2 Mbytes flash, 128 Kbytes SRAM, same package and peripheral set | Higher code storage capacity for complex protocol stacks or OTA update partitions | Select when firmware size exceeds 1.5 Mbytes or dual-bank flash update architecture is required |
| R5F563NJHDFB#V0 | 1.5 Mbytes flash, 256 Kbytes SRAM, same package and peripheral set | Increased RAM for large Ethernet frame buffering, real-time OS task stacks, or USB audio streaming | Select when application requires >128 Kbytes SRAM for RTOS heap, TCP/IP stack buffers, or graphics framebuffer |
Compared with R5F563NDCDFB#V0, R5F563NECDFB#V0 offers greater flash headroom for feature-rich firmware, while R5F563NJHDFB#V0 provides double the SRAM for memory-intensive networking or multimedia tasks-both retain identical Ethernet, USB, CAN, and safety features in the same 144-pin LQFP footprint.
Availability
R5F563NDCDFB#V0 is available at Aetrix Electronics and suitable for industrial gateways, PLC communication modules, building automation controllers, and medical connectivity hubs requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for R5F563NDCDFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group is engineered for high-performance, safety-certifiable embedded applications demanding integrated Ethernet, real-time determinism, and hardware security-targeting industrial automation, energy infrastructure, and networked medical devices.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563NDCDFB#V0?
The R5F563NDCDFB#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance. Its 32-bit RX CPU core includes a single-precision IEEE-754 floating-point unit, 5-stage pipeline, and variable-length instruction set. This enables deterministic real-time execution for industrial control loops, protocol stack processing, and sensor fusion algorithms without external coprocessors.
Does the R5F563NDCDFB#V0 support Ethernet connectivity, and what interface standards does it implement?
Yes, the R5F563NDCDFB#V0 integrates a full-featured Ethernet MAC supporting both 10 and 100 Mbps operation in full- and half-duplex modes. It implements IEEE 802.3-compliant MII and RMII physical layer interfaces, Magic Packet™ wake-on-LAN detection, and IEEE 802.3x flow control. An associated EDMAC controller with 2 Kbyte Tx/Rx FIFOs enables zero-copy frame handling and reduces CPU overhead during high-throughput network traffic.
What safety and security features are built into the R5F563NDCDFB#V0 for certified applications?
The R5F563NDCDFB#V0 includes hardware features required for IEC60730 Class B compliance: oscillation-stop detection, hardware CRC calculator (with three polynomials), independent watchdog timer (IWDT) driven by a dedicated LOCO clock, and self-diagnostic capability for the 10-bit A/D converter. It also integrates a Data Encryption Unit (DEU) supporting AES-128/192/256 encryption/decryption in ECB and CBC modes for secure firmware updates and data-at-rest protection.
How much on-chip memory does the R5F563NDCDFB#V0 provide, and what are its access characteristics?
The R5F563NDCDFB#V0 includes 1.5 Mbytes of on-chip flash memory accessible at 100 MHz with zero wait states, 128 Kbytes of SRAM also operating at 100 MHz with no wait states, and 32 Kbytes of data flash rated for 100,000 program/erase cycles. Flash supports on-board programming via SWD/FINE and off-board parallel programming (for ≥100-pin packages). SRAM retains data in deep software standby mode when backed by VBATT.
What is the package type and pin count of the R5F563NDCDFB#V0, and how many I/O pins are available?
The R5F563NDCDFB#V0 is housed in a 144-pin LQFP package (PLQP0144KA-A), measuring 20 × 20 mm with 0.5 mm pitch. It provides 111 general-purpose I/O pins, including 18 pins with 5-V tolerance, configurable pull-up resistors, and open-drain output capability. The pinout supports dedicated Ethernet (MII/RMII), USB 2.0, CAN, multiple SCI/I²C/RSPI channels, and 21-channel 12-bit A/D inputs-all accessible without multiplexing conflicts in standard configurations.
R5F563NDCDFB#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NDCDFB#V0 FAQ
1.How can I place an order for R5F563NDCDFB#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NDCDFB#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NDCDFB#V0 reliable?
The price and inventory of R5F563NDCDFB#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NDCDFB#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NDCDFB#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NDCDFB#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NDCDFB#V0?
R5F563NDCDFB#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NDCDFB#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NDCDFB#V0?
For technical support, including R5F563NDCDFB#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NDCDFB#V0 requirements.
6.How does Aetrix verify that R5F563NDCDFB#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NDCDFB#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NDCDFB#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NDCDFB#V0?
All R5F563NDCDFB#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NDCDFB#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NDCDFB#V0 part is unused and in its original packaging.
Return procedure for R5F563NDCDFB#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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