Renesas R5F563NECDBG#U0
- Part No.:
- R5F563NECDBG#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F563NECDBG#U0.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563NECDBG#U0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 2 Mbyte on-chip flash, 128 Kbyte SRAM, and 32 Kbyte data flash. It features 134 general-purpose I/O pins (18 with 5-V tolerance), hardware AES encryption (DEU), and operates from 2.7–3.6 V across –40 to +85°C. Used in industrial gateways requiring deterministic real-time control and network connectivity.
For engineers reviewing the R5F563NECDBG#U0 datasheet, R5F563NECDBG#U0 pinout, R5F563NECDBG#U0 application, or R5F563NECDBG#U0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 100-MHz deterministic timing, integrated DEU for secure firmware updates, and compatibility with Renesas E20/E1 debug interfaces.
Technical Context
The R5F563NECDBG#U0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, supporting 165 DMIPS at 100 MHz and IEEE-754 single-precision floating-point operations. Its memory subsystem includes zero-wait-state 100-MHz flash and SRAM, plus background-programmable 32-Kbyte data flash rated for 100,000 erase/write cycles.
It integrates dedicated peripherals for industrial networking: Ethernet controller (10/100 Mbps, MII/RMII), three CAN 2.0B modules (32 mailboxes each), full-speed USB 2.0 host/function/OTG, and four I²C interfaces (one FM+). Power management includes four low-power modes and RTC operation from dedicated VBATT supply (2.3–3.6 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard, 100 MHz max, 165 DMIPS, IEEE-754 FPU |
| Memory | 2 Mbyte flash (no wait states @ 100 MHz), 128 Kbyte SRAM, 32 Kbyte data flash (100k cycles) |
| Networking | Ethernet MAC (10/100 Mbps, MII/RMII), 3× CAN 2.0B (32 mailboxes each), USB 2.0 FS host/function/OTG |
| Analog Peripherals | 21-channel 12-bit A/D (1 μs conversion), 8-channel 10-bit A/D, 2× 10-bit D/A, on-die temperature sensor (±1°C) |
| Security & Timing | AES-128/192/256 (ECB/CBC) via DEU, RTC with battery backup, independent watchdog (IWDT), MPU |
| Package & Environment | PLBG0176GA-A (176-pin LFBGA, 13 × 13 mm, 0.8-mm pitch), –40 to +85°C (D version) |
| I/O & Power | 134 GPIO (18× 5-V tolerant), 2.7–3.6 V supply, 500 μA/MHz active current, four low-power modes |
Pinout & Package
Package: PLBG0176GA-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 13 × 13 mm body, 0.8 mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated power domains for core (VCC), analog (AVCC0), USB (VCC_USB), and backup (VBATT); decoupling required per Renesas layout guidelines |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables PLL-based 100 MHz system clock with ±0.5% stability over temp/voltage |
| MD[0:3] | Mode selection pins | Configure boot source (ROM/flash), debug interface (JTAG/FINE), and reset behavior at power-on |
| ETXD[0:3], ETX_EN, ETX_ER, ERXD[0:3], ERX_DV, ERX_ER | Ethernet PHY interface (MII) | Direct connection to external 10/100 PHY; supports RMII with reduced pin count when MDIO/MDC used instead |
| USB_VBUS, USB_DP, USB_DM | USB 2.0 physical interface | Full-speed (12 Mbps) transceiver with internal termination; VBUS sensing enables host/device role negotiation |
| MTIOC[0:5]A/B, TIOCA[0:5]/TIOCB[0:5] | Timer waveform I/O | Hardware PWM, input capture, and phase-counting outputs for motor control and encoder interfacing |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Dedicated DMA engine offloads packet processing; 2 KB TX/RX FIFOs enable interrupt coalescing and low-CPU-load TCP/IP stack operation |
| Hardware AES-128/192/256 | DEU unit performs encryption/decryption in <100 cycles per block; enables secure OTA firmware updates without software overhead |
| 12-bit A/D with S&H | Simultaneous sampling across 21 channels with 1.0 μs conversion time at 50 MHz PCLK; supports triggered acquisition from MTU/TPU timers |
| Flexible Clock System | Independent programmable dividers for ICLK (CPU), PCLK (peripherals), FCLK (flash), and BCLK (external bus); enables precise power/performance tuning |
| IEC 60730 Support | Built-in oscillation-stop detection, CRC calculator, self-diagnostic A/D, and IWDT meet Class B functional safety requirements for appliance control |
Applications
| Industrial Ethernet Gateway | Secure PLC Controller |
|---|---|
|
Use Scenario: Edge gateway aggregating Modbus TCP, EtherNet/IP, and PROFINET traffic between field devices and cloud SCADA systems. IC Role / Device Role / Timing Role: Primary MCU executing real-time protocol stacks, managing dual Ethernet ports, and performing deterministic I/O scanning. Use Value: Integrated Ethernet MAC + EDMAC reduces external component count; 100 MHz CPU ensures sub-1 ms cycle times for motion control loops. |
Use Scenario: Safety-rated programmable logic controller with encrypted firmware storage and runtime integrity checks. IC Role / Device Role / Timing Role: Main controller executing IEC 61131-3 logic, validating signed firmware images, and monitoring hardware faults. Use Value: On-chip DEU enables AES-256 decryption of firmware updates; built-in CRC and IWDT satisfy IEC 60730 Class B compliance without external ICs. |
| Human Machine Interface (HMI) | Networked Energy Meter |
|
Use Scenario: Touch-enabled panel PC with local graphics rendering and remote configuration via web server. IC Role / Device Role / Timing Role: Application processor running RTOS, driving TFT LCD via EXDMAC, and serving HTTP pages over Ethernet/USB. Use Value: EXDMAC's cluster transfer mode enables direct frame buffer writes to LCD; USB OTG allows field technician firmware recovery via USB stick. |
Use Scenario: DIN-rail mounted smart meter transmitting consumption data via Ethernet and cellular fallback. IC Role / Device Role / Timing Role: Data concentrator acquiring ADC samples from shunt/sensor front-end, timestamping with RTC, and buffering for network transmission. Use Value: 21-channel 12-bit A/D with sample-and-hold captures synchronized voltage/current waveforms; RTC battery backup maintains time during mains outage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDFC#U0 | LQFP-176 package (PLQP0176KB-A, 24 × 24 mm, 0.5 mm pitch); identical flash/SRAM/peripherals | Better thermal dissipation and hand-solderability; requires larger PCB area and different layout constraints | Select for prototyping, manual assembly, or environments where BGA rework is impractical |
| R5F563NEDDBG#U0 | Same LFBGA-176 package but with 2 Mbyte flash, 128 Kbyte SRAM, and identical peripheral set | No functional difference; differs only in factory-programmed flash content and security settings | Select when pre-flashed bootloader or certified secure image is required from factory |
Compared with R5F563NECDBG#U0, the LQFP alternative offers easier inspection and rework at the cost of board space, while the R5F563NEDDBG#U0 variant provides identical hardware functionality with differentiated firmware provisioning-enabling scalable secure boot deployment across product SKUs.
Availability
R5F563NECDBG#U0 is available at Aetrix Electronics and suitable for industrial gateways, secure PLC controllers, HMIs, and networked energy meters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F563NECDBG#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group targets industrial automation and networked embedded systems, integrating Ethernet, USB, CAN, and security accelerators into a single high-performance 32-bit MCU platform optimized for deterministic real-time operation.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563NECDBG#U0?
The R5F563NECDBG#U0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS using the 32-bit RX CPU core. It includes a single-precision IEEE-754 floating-point unit and two multiply-accumulate units, enabling efficient signal processing and control algorithm execution. The R5F563NECDBG#U0 achieves this performance with zero-wait-state access to both flash and SRAM.
Does the R5F563NECDBG#U0 support Ethernet connectivity, and what interfaces are available?
Yes, the R5F563NECDBG#U0 integrates a full-featured Ethernet MAC compliant with IEEE 802.3, supporting 10/100 Mbps in full- and half-duplex modes. It supports both MII and RMII physical layer interfaces, Magic Packet™ wake-on-LAN, and IEEE 802.3x flow control. The dedicated EDMAC peripheral handles descriptor-based packet transfers to reduce CPU load. The R5F563NECDBG#U0 does not include a PHY; an external PHY is required.
What security features are implemented in the R5F563NECDBG#U0 for firmware protection?
The R5F563NECDBG#U0 includes a Data Encryption Unit (DEU) supporting AES-128/192/256 encryption and decryption in ECB and CBC modes. It also features a Memory Protection Unit (MPU), register write protection, and IEC 60730-compliant self-test functions including CRC calculation and A/D converter diagnostics. These features enable secure boot, encrypted firmware updates, and runtime integrity verification in the R5F563NECDBG#U0.
What are the memory resources available on the R5F563NECDBG#U0?
The R5F563NECDBG#U0 includes 2 Mbyte of on-chip flash memory (accessible at 100 MHz with no wait states), 128 Kbyte of zero-wait-state SRAM, and 32 Kbyte of reprogrammable data flash rated for 100,000 erase/write cycles. The flash supports on-board programming via SWD/JTAG and off-board parallel programming. The R5F563NECDBG#U0 also supports external bus expansion with up to eight 16-Mbyte CS areas and a dedicated 128-Mbyte SDRAM interface.
Which development tools and debug interfaces are supported by the R5F563NECDBG#U0?
The R5F563NECDBG#U0 supports Renesas E1 and E20 debug emulators via JTAG and FINE (two-wire) interfaces. It is compatible with e2 studio IDE, CS+ (formerly High-performance Embedded Workshop), and GCC-based toolchains. The device includes on-chip debugging circuitry, breakpoint/watchpoint units, and real-time trace capabilities. The R5F563NECDBG#U0 also supports flash programming and debugging over USB using the integrated USB 2.0 function controller.
R5F563NECDBG#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NECDBG#U0 FAQ
1.How can I place an order for R5F563NECDBG#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NECDBG#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NECDBG#U0 reliable?
The price and inventory of R5F563NECDBG#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NECDBG#U0 is usually 5 days.
3.What payment methods are accepted for R5F563NECDBG#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NECDBG#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NECDBG#U0?
R5F563NECDBG#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NECDBG#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NECDBG#U0?
For technical support, including R5F563NECDBG#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NECDBG#U0 requirements.
6.How does Aetrix verify that R5F563NECDBG#U0 is sourced from the original manufacturer or authorized distributors?
All R5F563NECDBG#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NECDBG#U0 meets industry standards.
7.What is the process for return or replacement of R5F563NECDBG#U0?
All R5F563NECDBG#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NECDBG#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NECDBG#U0 part is unused and in its original packaging.
Return procedure for R5F563NECDBG#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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