My Inquiry
My Account
Renesas R5F563NEDGFC#V0
- Part No.:
- R5F563NEDGFC#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F563NEDGFC#V0.pdf
- Description:
- 32BIT MCU RX63N
- Quantity:
- Payment:
- Shipping:
Inventory:4,653
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563NEDGFC#V0 from Renesas is a 100-MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 2 MB on-chip flash, 128 KB SRAM, and 32 KB data flash. It features 134 general-purpose I/O pins (5-V tolerant), hardware AES encryption (DEU), and operates from 2.7–3.6 V across –40 to +85°C. Used in industrial gateways requiring deterministic real-time control, networked HMI, and secure firmware updates.
For engineers reviewing the R5F563NEDGFC#V0 datasheet, R5F563NEDGFC#V0 pinout, R5F563NEDGFC#V0 application, or R5F563NEDGFC#V0 equivalent, key selection criteria include Ethernet MAC support (MII/RMII), 100-MHz CPU performance (165 DMIPS), dual A/D converters (21×12-bit + 8×10-bit), USB 2.0 host/function/OTG capability, and IEC60730 safety features including CRC, self-diagnostic A/D, and oscillation-stop detection.
Technical Context
The R5F563NEDGFC#V0 implements the CISC Harvard-architecture RX CPU core with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU). It integrates dedicated peripherals for industrial connectivity: Ethernet controller (ETHERC) with EDMAC DMA, USB 2.0 host/function module (USBa), three CAN channels (ISO11898-1), and four RIIC interfaces (up to 1 Mbps).
Its timing subsystem includes RTC with battery backup, independent watchdog timer (IWDT) driven by dedicated 125-kHz LOCO, and multiple timer units (MTU2, TPU, TMR, CMT) supporting PWM generation, input capture, phase counting, and A/D trigger synchronization - all configurable via register write protection for functional safety compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RX 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS, IEEE-754 single-precision FPU |
| Memory | 2 MB on-chip flash (no wait states @100 MHz), 128 KB SRAM, 32 KB reprogrammable data flash (100k cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG, 3× CAN, 13× SCI, 4× I2C, 3× SPI, 1× IEBus |
| Analog Peripherals | 21-channel 12-bit A/D (1 µs conversion), 8-channel 10-bit A/D, 2-channel 10-bit D/A, on-die temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256 (ECB/CBC) via DEU, CRC calculator, IWDT, oscillation-stop detection, A/D self-diagnostic |
| Power & Environment | 2.7–3.6 V supply, -40 to +85°C operating range, four low-power modes, RTC battery backup support |
| Package & I/O | 176-pin LQFP (PLQP0176KB-A, 24×24 mm, 0.5 mm pitch), 134 GPIO (5-V tolerant, open-drain, pull-up) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 mm × 24 mm, 0.5 mm pitch, exposed pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual 2.7–3.6 V core/analog supply domains; dedicated AVCC0 and VREFH pins ensure stable ADC reference |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables PLL-based 100 MHz system clock with programmable frequency division |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3u-compliant MDIO bus for PHY configuration and status monitoring |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII interface signals; RMII mode uses reduced pin count (TXD[1:0], RXD[1:0], TX_EN, CRS_DV, REF_CLK) |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical interface | Full-speed (12 Mbps) transceiver with internal termination; VBUS sensing enables host/device role negotiation |
| AD00–AD20 | Analog input channels | 21 dedicated 12-bit A/D inputs with shared sample-and-hold; supports simultaneous sampling and conversion result addition |
| DA0 / DA1 | Digital-to-analog outputs | 2× 10-bit voltage-output DACs referenced to VREFH; used for analog waveform generation or sensor calibration |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Dedicated DMA engine offloads frame processing; 2 KB Tx/Rx FIFOs enable zero-copy packet handling in RTOS environments |
| USB 2.0 Host/Function/OTG | Single-port dual-role controller with 2 KB on-chip RAM buffer; supports CDC, HID, and MSC class drivers without external memory |
| IEC60730 Safety Support | Hardware-accelerated CRC, A/D self-test, clock failure detection, and MPU-enforced memory partitioning meet Class B requirements |
| Flexible Timer System | MTU2 (6-channel), TPU (12-channel), TMR (4-channel), CMT (4-channel) provide synchronized PWM, encoder input, and A/D trigger generation |
| Data Encryption Unit (DEU) | Hardware AES engine processes 128/192/256-bit keys in ECB/CBC modes at >10 MB/s throughput; reduces firmware update latency and memory footprint |
Applications
| Industrial Ethernet Gateway | Secure Networked HMI |
|---|---|
|
Use Scenario: Protocol translation between Modbus TCP, EtherNet/IP, and fieldbus devices in factory automation. IC Role / Device Role / Timing Role: Central MCU executing real-time protocol stacks, managing Ethernet/USB/CAN interfaces, and synchronizing I/O via MTU2-triggered A/D sampling. Use Value: Integrated ETHERC + EDMAC eliminates external PHY+DMA complexity; 100 MHz CPU ensures sub-10 ms cycle times for motion control coordination. |
Use Scenario: Touch-enabled operator panel with encrypted firmware updates and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Application processor running embedded Linux or FreeRTOS, driving TFT LCD via EXDMAC, securing OTA updates with DEU, and logging events via RTC timestamping. Use Value: On-chip 2 MB flash stores full UI assets and signed firmware images; hardware AES accelerates signature verification without CPU overhead. |
| Smart Energy Meter Hub | Medical Device Controller |
|
Use Scenario: Multi-tariff electricity meter aggregating data from CT sensors, optical port, and cellular modem. IC Role / Device Role / Timing Role: Precision measurement controller using 12-bit A/D with sample-and-hold for anti-aliasing, RTC for billing intervals, and USB for field calibration. Use Value: Temperature-compensated A/D (±1°C sensor) maintains accuracy across ambient ranges; battery-backed RTC retains time during power loss. |
Use Scenario: Infusion pump controller requiring IEC 62304 compliance, fault logging, and audible alarm generation. IC Role / Device Role / Timing Role: Safety-critical controller executing dual-core lockstep logic (via software partitioning), monitoring motor current via 10-bit A/D, and generating PWM-driven piezo alerts. Use Value: IWDT + oscillation-stop detection prevents runaway execution; CRC calculator validates configuration EEPROM before actuation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDGFC#V0 | Same package and pinout; differs only in flash size (2 MB vs. 2 MB), but ROM version lacks ROM-less boot flexibility | No Ethernet MAC; limited to non-networked control applications | Select R5F563NEDGFC#V0 when Ethernet connectivity and full peripheral set are required; R5F563NECDGFC#V0 is not applicable due to missing ETHERC. |
| R5F566NHDFC#V0 (RX66N) | Successor family: 160 MHz CPU, 4 MB flash, enhanced security (TRNG, secure boot), same 176-LQFP package | Higher performance and extended safety certification (IEC 61508 SIL3-ready); requires minor clock/peripheral register updates | R5F566NHDFC#V0 offers migration path for future-proofing; R5F563NEDGFC#V0 remains optimal for cost-sensitive, Ethernet-dependent designs with mature toolchain support. |
Compared with R5F563NECDGFC#V0 (non-Ethernet variant) and R5F566NHDFC#V0 (RX66N successor), the R5F563NEDGFC#V0 uniquely balances proven Ethernet integration, IEC60730 safety features, and production-ready ecosystem - making it the most direct fit for industrial gateway designs requiring no layout change or firmware rewrite.
Availability
R5F563NEDGFC#V0 is available at Aetrix Electronics and suitable for industrial gateways, networked HMIs, smart energy meters, and medical device controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563NEDGFC#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX63N Group was designed for real-time industrial control with integrated Ethernet, USB, and safety features - targeting applications where deterministic response, network connectivity, and functional safety coexist in resource-constrained environments.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563NEDGFC#V0?
The R5F563NEDGFC#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using the 32-bit RX CPU core. Its single-precision IEEE-754 floating-point unit (FPU) and dual multiply-accumulate units enable efficient signal processing and control loop execution. This performance level is validated under worst-case voltage (2.7 V) and temperature (85°C) conditions per Renesas specification R01DS0098EJ0180.
Does the R5F563NEDGFC#V0 support Ethernet connectivity, and what interface modes are available?
Yes, the R5F563NEDGFC#V0 includes a fully integrated Ethernet MAC (ETHERC) compliant with IEEE 802.3 and 802.3u standards. It supports both MII (Media Independent Interface) and RMII (Reduced MII) modes at 10/100 Mbps full- or half-duplex operation. The dedicated EDMAC controller handles descriptor-based frame transfers, reducing CPU load during high-throughput network traffic - a capability confirmed in the RX63N Group hardware manual.
What analog peripherals are integrated into the R5F563NEDGFC#V0, and how are they configured?
The R5F563NEDGFC#V0 integrates a 21-channel 12-bit A/D converter (S12ADa) with sample-and-hold, an 8-channel 10-bit A/D converter (ADb), two 10-bit D/A converters (DAa), and an on-die temperature sensor (±1°C accuracy). Conversion can be triggered by software, timers (MTU2/TPU/TMR), or external signals. The 12-bit A/D supports result addition for noise reduction, and both A/D units include self-diagnostic functions required for IEC60730 Class B compliance.
How does the R5F563NEDGFC#V0 support functional safety standards like IEC60730?
The R5F563NEDGFC#V0 includes hardware features explicitly cited for IEC60730 compliance: oscillation-stoppage detection, hardware CRC calculator (with selectable polynomials), independent watchdog timer (IWDT) driven by dedicated LOCO, self-diagnostic A/D functionality, and memory protection unit (MPU) for runtime memory access control. These capabilities are documented in Section 1.1 of the RX63N Group datasheet R01DS0098EJ0180 and validated in Renesas' IEC60730 safety manual.
What is the package type and pin count of the R5F563NEDGFC#V0, and are the I/O pins 5-V tolerant?
The R5F563NEDGFC#V0 is packaged in a 176-pin LQFP (PLQP0176KB-A), measuring 24 mm × 24 mm with 0.5 mm pitch. It provides 134 general-purpose I/O pins, all of which support 5-V tolerance, open-drain output, and programmable pull-up resistors. Eighteen of these pins are designated as 5-V tolerant - a specification confirmed in Table 1.2 of the RX63N Group datasheet and verified on Renesas' official product page for this part number.
R5F563NEDGFC#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NEDGFC#V0 FAQ
1.How can I place an order for R5F563NEDGFC#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NEDGFC#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NEDGFC#V0 reliable?
The price and inventory of R5F563NEDGFC#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NEDGFC#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NEDGFC#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NEDGFC#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NEDGFC#V0?
R5F563NEDGFC#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NEDGFC#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NEDGFC#V0?
For technical support, including R5F563NEDGFC#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NEDGFC#V0 requirements.
6.How does Aetrix verify that R5F563NEDGFC#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NEDGFC#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NEDGFC#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NEDGFC#V0?
All R5F563NEDGFC#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NEDGFC#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NEDGFC#V0 part is unused and in its original packaging.
Return procedure for R5F563NEDGFC#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563NEDGFC#V0 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
