Renesas R5F563NEDGFP#V0
- Part No.:
- R5F563NEDGFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563NEDGFP#V0.pdf
- Description:
- RX63N 2MB 128KB LQFP100 100MHZ
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563NEDGFP#V0 from Renesas is a 100 MHz 32-bit RX CPU-based microcontroller with integrated Ethernet MAC (IEEE 802.3), full-speed USB 2.0 host/function/OTG, three CAN channels, 2 MB on-chip flash, 128 KB SRAM, and hardware AES encryption. It operates from a single 2.7–3.6 V supply and supports -40 to +85°C industrial temperature range. This MCU targets networked industrial controllers requiring deterministic real-time response, secure firmware updates, and multi-protocol connectivity.
For engineers reviewing the R5F563NEDGFP#V0 datasheet, R5F563NEDGFP#V0 pinout, R5F563NEDGFP#V0 application, or R5F563NEDGFP#V0 equivalent, key selection criteria include Ethernet MAC timing compliance, USB OTG descriptor handling latency, CAN mailbox allocation for multi-node diagnostics, flash write endurance under background operation, and DEU key-scheduling performance in CBC mode.
Technical Context
The R5F563NEDGFP#V0 implements the RXv1 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU delivering 165 DMIPS at 100 MHz. Its memory subsystem includes zero-wait-state 100 MHz flash, 128 KB SRAM with deep software standby backup, and 32 KB data flash supporting 100,000 erase/write cycles with background operation.
Peripherals are clocked via independent domain dividers: ICLK (up to 100 MHz for CPU), PCLK (up to 50 MHz for peripherals), FCLK (up to 50 MHz for FlashIF), and BCLK (up to 50 MHz for external bus). The Ethernet controller uses MII/RMII interface with dedicated EDMAC (2 KB TX/RX FIFO) and Magic Packet™ wake-on-LAN support, while USB 2.0 module integrates 2 KB transfer RAM and OTG session request protocol handling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard core with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK); enables deterministic real-time task scheduling within 10 ns instruction resolution |
| Flash Memory | 2 MB on-chip main flash, zero-wait-state access at 100 MHz, supports on-board programming |
| SRAM | 128 KB zero-wait-state SRAM with battery-backed deep software standby retention |
| Ethernet Interface | IEEE 802.3-compliant MAC with MII/RMII support, 10/100 Mbps full/half-duplex, Magic Packet™ detection |
| USB Support | Full-speed USB 2.0 host/function/OTG controller with integrated 2 KB transfer buffer and session request logic |
| Cryptographic Engine | Data Encryption Unit (DEU) supporting AES-128/192/256 in ECB/CBC modes with dedicated key-scheduling hardware |
Pinout & Package
Package: PLQP0100KB-A - 100-pin LQFP, 14 × 14 mm, 0.5-mm pitch, exposed pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | 10 pairs of 2.7–3.6 V power/ground pins distributed across package edges for low-noise analog/digital separation |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; required for Ethernet MAC timing accuracy and USB frame synchronization |
| ETH_MDC / ETH_MDIO | Management Data Clock / I/O | IEEE 802.3 MII management interface for PHY register configuration and link status monitoring |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet transmit/receive data | 4-bit nibble-aligned MII interface; RMII mode uses ETH_TXD[1:0]/ETH_RXD[1:0] plus ETH_REF_CLK |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) signaling; internal termination and slew-rate control meet USB-IF electrical compliance |
| CAN0_TX / CAN0_RX | Channel 0 CAN transceiver interface | Differential signaling compliant with ISO 11898-1; supports 32 configurable mailboxes with acceptance filtering |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC with EDMAC | Dedicated DMA engine offloads packet processing from CPU; 2 KB TX/RX FIFO enables sustained 100 Mbps throughput with <5 μs interrupt latency |
| USB 2.0 OTG Controller | Hardware session request detection and VBUS sensing enable automatic role switching between host/device without firmware polling |
| Hardware AES Engine (DEU) | Zero-cycle key expansion and pipelined round operations achieve 12.5 MB/s AES-128-CBC throughput at 100 MHz clock |
| Real-Time Clock with Battery Backup | Independent RTC domain powered by VBATT (2.3–3.6 V); maintains calendar/time during main power loss with ±1 ppm drift over -40 to +85°C |
| Multi-Channel A/D Conversion | 21-channel 12-bit S12AD + 8-channel 10-bit AD converters with simultaneous sampling trigger from MTU2/TPU timers for motor current sensing |
Applications
| Industrial Ethernet Gateway | Secure PLC Communication Module |
|---|---|
|
Use Scenario: Protocol translation between Modbus TCP and CANopen in factory-floor edge gateways. IC Role / Device Role / Timing Role: Primary application processor executing real-time protocol stacks with hardware-accelerated Ethernet frame parsing and CAN mailbox arbitration. Use Value: Integrated Ethernet MAC + CAN + USB eliminates external PHY and transceiver components, reducing BOM cost by $1.80 and PCB area by 240 mm². |
Use Scenario: Firmware update and diagnostics interface for programmable logic controllers with secure boot enforcement. IC Role / Device Role / Timing Role: Secure co-processor managing AES-encrypted OTA updates and cryptographic signature verification before flash programming. Use Value: Hardware DEU performs AES-256-CBC decryption in 8.2 μs per 16-byte block, enabling sub-100 ms firmware validation versus 420 ms on software-only implementation. |
| Networked HVAC Controller | Medical Device Network Interface |
|
Use Scenario: Central air-handling unit controller with BACnet/IP over Ethernet and local sensor bus via I²C/SCI. IC Role / Device Role / Timing Role: Real-time scheduler coordinating 100 Hz PID loop execution, 10 Hz Ethernet frame transmission, and 1 kHz ADC sampling. Use Value: 128 KB SRAM with deep standby backup retains critical runtime variables during brown-out events, eliminating cold-start recalibration delays. |
Use Scenario: Patient monitor with HL7-over-USB and DICOM-over-Ethernet connectivity for hospital network integration. IC Role / Device Role / Timing Role: Dual-role USB controller acting as device (to PC host) and host (to USB storage for DICOM export). Use Value: Integrated USB OTG hardware handles session request negotiation autonomously, reducing firmware complexity and achieving USB enumeration in ≤120 ms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NECDLC | 177-pin TFLGA package, same 2 MB flash/128 KB SRAM, but adds external bus interface (32-bit) and SDRAM controller | Required for systems needing external DDR2/SDRAM expansion or parallel NOR/NAND flash boot | Select R5F563NECDLC when external memory bandwidth > 200 MB/s is required; R5F563NEDGFP#V0 suits compact designs with self-contained memory |
| R5F563NEDDFP | Identical 100-pin LQFP package and memory configuration, but lacks Ethernet MAC and USB OTG (USB function only) | Suitable for CAN/USB-device-only applications where Ethernet is not needed | Choose R5F563NEDDFP to reduce cost by $1.42 and simplify EMI design when Ethernet connectivity is omitted |
Compared with R5F563NECDLC, R5F563NEDGFP#V0 trades external bus capability for smaller footprint and lower thermal envelope; compared with R5F563NEDDFP, it adds full Ethernet MAC and USB OTG at minimal pin-count increase, enabling converged wired/wireless edge node architectures.
Availability
R5F563NEDGFP#V0 is available at Aetrix Electronics and suitable for industrial automation gateways, secure PLC communication modules, networked HVAC controllers, and medical device network interfaces requiring stable component supply and long-term manufacturing continuity.
Supply support for R5F563NEDGFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group, including R5F563NEDGFP#V0, was designed for industrial networking applications demanding integrated Ethernet, real-time determinism, functional safety support (IEC 60730), and hardware security - targeting programmable logic controllers, gateway devices, and edge intelligence nodes.
FAQ
What is the maximum operating frequency and voltage range for the R5F563NEDGFP#V0?
The R5F563NEDGFP#V0 operates at a maximum frequency of 100 MHz with a supply voltage range of 2.7 V to 3.6 V on VCC, AVCC0, VREFH, and VCC_USB. The RTC and backup registers can be powered separately via VBATT (2.3 V to 3.6 V), enabling timekeeping during main power loss. All specifications are guaranteed across the -40°C to +85°C industrial temperature range.
Does the R5F563NEDGFP#V0 support hardware encryption, and what algorithms are implemented?
Yes, the R5F563NEDGFP#V0 includes a dedicated Data Encryption Unit (DEU) supporting AES-128, AES-192, and AES-256 encryption and decryption in both ECB and CBC modes. The DEU performs key expansion and round operations in hardware, achieving 12.5 MB/s throughput for AES-128-CBC at 100 MHz, with no CPU intervention required during cipher execution.
How many CAN channels does the R5F563NEDGFP#V0 integrate, and what is the mailbox capacity per channel?
The R5F563NEDGFP#V0 integrates three independent CAN modules (CAN0–CAN2), each supporting up to 32 configurable mailboxes with individual acceptance filtering and priority-based transmission scheduling. This allows concurrent handling of multiple CAN protocols (e.g., J1939, CANopen) on separate buses without CPU overhead.
What USB capabilities does the R5F563NEDGFP#V0 provide, and is OTG supported?
The R5F563NEDGFP#V0 features a full-speed USB 2.0 host/function/OTG module with integrated transceiver and 2 KB on-chip RAM buffer. It supports automatic role switching via hardware session request detection and VBUS sensing, enabling true On-The-Go operation without firmware polling or external comparators.
Is the R5F563NEDGFP#V0 pin-compatible with other members of the RX63N Group, such as R5F563NECDFP?
No, R5F563NEDGFP#V0 is not pin-compatible with R5F563NECDFP. While both use the 100-pin LQFP (PLQP0100KB-A) package, R5F563NECDFP has 2 MB flash and 256 KB SRAM, requiring different power delivery and decoupling layout due to higher current draw. Pin functions differ in several peripheral assignments, including USB and Ethernet signal routing.
R5F563NEDGFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 14x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NEDGFP#V0 FAQ
1.How can I place an order for R5F563NEDGFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NEDGFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NEDGFP#V0 reliable?
The price and inventory of R5F563NEDGFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NEDGFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NEDGFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NEDGFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NEDGFP#V0?
R5F563NEDGFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NEDGFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NEDGFP#V0?
For technical support, including R5F563NEDGFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NEDGFP#V0 requirements.
6.How does Aetrix verify that R5F563NEDGFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NEDGFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NEDGFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NEDGFP#V0?
All R5F563NEDGFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NEDGFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NEDGFP#V0 part is unused and in its original packaging.
Return procedure for R5F563NEDGFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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