My Inquiry
My Account
Renesas R5F563NWDGFB#V0
- Part No.:
- R5F563NWDGFB#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F563NWDGFB#V0.pdf
- Description:
- 32BIT MCU RX63N
- Quantity:
- Payment:
- Shipping:
Inventory:1,891
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563NWDGFB#V0 from Renesas is a 100-MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 165 DMIPS performance, 1 MB on-chip flash memory, and 192 KB SRAM. It operates from a 2.7–3.6 V supply, supports -40 to +105°C (G version), and targets industrial networking, gateway, and embedded control applications requiring real-time connectivity and cryptographic acceleration.
For engineers reviewing the R5F563NWDGFB#V0 datasheet, R5F563NWDGFB#V0 pinout, R5F563NWDGFB#V0 application, or R5F563NWDGFB#V0 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-A (144-pin LQFP), confirmed Ethernet/USB/CAN interface support, and validated alternative MCU options for migration or second-sourcing.
Technical Context
The R5F563NWDGFB#V0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, variable-length instructions, and hardware FPU compliant with IEEE-754 single-precision. Its clock system integrates PLL, HOCO (50 MHz), LOCO (125 kHz), and subclock oscillator - enabling independent ICLK (100 MHz), PCLK (50 MHz), FCLK (50 MHz), and BCLK (50 MHz) domains.
It features dedicated peripherals including an Ethernet controller (MII/RMII, 10/100 Mbps), USB 2.0 host/function/OTG module, three CAN channels (ISO 11898-1), four RIIC interfaces (up to 1 Mbps), and dual A/D converters (21×12-bit + 8×10-bit). The DEU provides AES-128/192/256 encryption in ECB/CBC mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RX 32-bit CPU with 5-stage pipeline, 165 DMIPS @ 100 MHz |
| Max Operating Frequency | 100 MHz system clock (ICLK), enabling deterministic real-time execution |
| Flash Memory | 1 MB on-chip flash, zero-wait-state access at 100 MHz for deterministic code execution |
| SRAM | 192 KB on-chip SRAM, no wait states, supports instruction + data storage and deep software standby backup |
| Peripherals | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 host/function/OTG, 3× CAN, 4× I²C, 13× SCI, 3× RSPI |
| Analog Functions | 21-channel 12-bit A/D (1 µs conversion), 8-channel 10-bit A/D, 2-channel 10-bit D/A, on-die temperature sensor (±1°C) |
| Cryptographic Engine | Data Encryption Unit (DEU) supporting AES-128/192/256 in ECB/CBC modes |
Pinout & Package
Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm, 0.5 mm pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated analog/digital power pins; 133 I/O pins with 5-V tolerance on selected signals |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal for precise system timing and Ethernet synchronization |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY register configuration and status monitoring |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII interface signals; RMII mode uses subset (TXD0, TX_EN, RXD0, RX_ER, REF_CLK) |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) transceiver interface; supports host, function, and OTG roles |
| CAN0_TX / CAN0_RX | Channel 0 CAN transceiver interface | ISO 11898-1-compliant differential signaling; 32-mailbox FIFO per CAN channel |
| AD000 – AD020 | Analog input channels | 21 dedicated 12-bit A/D inputs with sample-and-hold; shared with GPIO ports |
| DA0 / DA1 | Digital-to-analog outputs | 2× 10-bit voltage-output DACs referenced to VREFH (2.7–3.6 V) |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Dedicated DMA controller offloads CPU during frame transmission/reception; 2 KB TX/RX FIFOs reduce interrupt overhead |
| USB 2.0 Host/Function/OTG | Single-port dual-role module with 2 KB on-chip RAM buffer; supports self-powered and bus-powered configurations |
| Real-Time Clock (RTC) | Battery-backed calendar/clock with alarm, periodic, and carry interrupts; operates down to 2.3 V on VBATT |
| Memory Protection Unit (MPU) | Configurable region-based protection for flash, SRAM, and peripheral registers to enforce secure firmware partitioning |
| IEC 60730 Safety Support | Integrated oscillation-stop detection, CRC calculator (3 polynomials), IWDT, and A/D self-diagnostic for Class B compliance |
| Low-Power Modes | Four modes (Sleep, All-module clock stop, Software standby, Deep software standby) with RTC and wakeup-capable peripherals retained |
Applications
| Industrial Gateway | Building Automation Controller |
|---|---|
Use Scenario: Edge node aggregating Modbus RTU, BACnet MS/TP, and KNX devices into Ethernet/IP or MQTT networks. IC Role / Device Role / Timing Role: Primary application processor with integrated Ethernet MAC, USB for field service, and CAN for legacy device bridging. Use Value: Eliminates external PHY and protocol bridge ICs; 192 KB SRAM enables concurrent protocol stacks and TLS handshake buffers. |
Use Scenario: HVAC controller managing zone sensors, actuators, and supervisory communication via BACnet/IP and LonWorks. IC Role / Device Role / Timing Role: Real-time control unit with deterministic timer units (MTU2, TPU), 12-bit A/D for thermistor readings, and RTC for scheduling. Use Value: On-chip 12-bit A/D with sample-and-hold ensures accurate temperature measurement; DEU enables secure firmware updates over BACnet/IP. |
| Smart Energy Meter | Medical Diagnostic Interface |
Use Scenario: DIN-rail meter with pulse counting, tariff switching, tamper detection, and DLMS/COSEM over Ethernet. IC Role / Device Role / Timing Role: Secure metering SoC with AES encryption (DEU), RTC for time-of-use billing, and isolated CAN for PLC communication. Use Value: Hardware-accelerated AES-128/192/256 meets IEC 62056-62 security requirements; 100 MHz core handles DLMS parsing without external co-processor. |
Use Scenario: Portable ultrasound or ECG front-end interfacing analog sensors, driving display, and transmitting DICOM over wired Ethernet. IC Role / Device Role / Timing Role: Signal acquisition and protocol gateway with 21-channel 12-bit A/D, parallel data capture (PDC), and USB OTG for PC tethering. Use Value: 1 µs A/D conversion enables high-fidelity waveform sampling; USB OTG allows direct firmware update and DICOM export without host PC drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NEDDFB#V0 | Same package (PLQP0144KA-A), identical peripherals, but 2 MB flash and 256 KB SRAM | Higher memory headroom for complex protocol stacks or OTA firmware images | Select when >1 MB flash is required for application + bootloader + secure update partition |
| R5F563NKDDFB#V0 | Same package, 2 MB flash, but only 192 KB SRAM and no Ethernet controller (RX631 Group) | Lacks Ethernet MAC and EDMAC; retains USB/CAN/I²C and same crypto engine | Choose for cost-sensitive non-networked control where Ethernet is unnecessary |
Compared with R5F563NWDGFB#V0, R5F563NEDDFB#V0 offers scalable memory for future-proofing, while R5F563NKDDFB#V0 removes Ethernet to reduce BOM cost - both maintain identical pinout, clock architecture, and safety features for seamless layout reuse.
Availability
R5F563NWDGFB#V0 is available at Aetrix Electronics and suitable for industrial gateways, building automation controllers, smart energy meters, and medical diagnostic interfaces requiring stable component supply, extended temperature operation (-40 to +105°C), and long-term lifecycle support.
Supply support for R5F563NWDGFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group is designed for industrial connectivity applications demanding integrated Ethernet, real-time performance, functional safety (IEC 60730), and hardware crypto - targeting gateways, HMIs, and edge controllers.
FAQ
What is the operating temperature range of the R5F563NWDGFB#V0?
The R5F563NWDGFB#V0 is a G-version device rated for -40 to +105°C ambient operation, making it suitable for industrial environments with elevated thermal stress. This rating applies to the full functional specification including Ethernet MAC, USB, and CAN modules - verified across the entire temperature range per Renesas R01DS0098EJ0180 datasheet.
Does the R5F563NWDGFB#V0 include an Ethernet physical layer (PHY)?
No, the R5F563NWDGFB#V0 integrates only the Ethernet Media Access Controller (MAC) and associated EDMAC DMA engine. An external PHY IC (e.g., DP83848, LAN8720) is required for MII or RMII physical layer signaling. The R5F563NWDGFB#V0 provides all necessary MAC control, descriptor management, and clocking signals per IEEE 802.3 standards.
How much SRAM and flash memory does the R5F563NWDGFB#V0 have?
The R5F563NWDGFB#V0 contains 192 KB of on-chip SRAM and 1 MB of on-chip flash memory. Both operate at zero wait states up to 100 MHz, enabling deterministic real-time execution. Flash supports background programming/erasing (BGO) and is reprogrammable over SWD/JTAG or via on-chip bootloader.
Is the R5F563NWDGFB#V0 pin-compatible with other RX63N Group MCUs in the same package?
Yes, the R5F563NWDGFB#V0 uses the PLQP0144KA-A (144-pin LQFP) package and shares identical pinout with all other RX63N Group devices in that package, including R5F563NEDDFB#V0 and R5F563NKDDFB#V0. Peripheral enablement varies by flash/SRAM configuration, but pin functions and electrical characteristics remain consistent.
What debugging interfaces does the R5F563NWDGFB#V0 support?
The R5F563NWDGFB#V0 supports both JTAG and FINE (two-wire) debugging interfaces, compatible with Renesas E1 and E20 emulators. These interfaces provide full SWD-style debug access, including halt/resume, memory inspection, register read/write, and real-time trace - essential for development of safety-critical industrial firmware.
R5F563NWDGFB#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NWDGFB#V0 FAQ
1.How can I place an order for R5F563NWDGFB#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NWDGFB#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NWDGFB#V0 reliable?
The price and inventory of R5F563NWDGFB#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NWDGFB#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NWDGFB#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NWDGFB#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NWDGFB#V0?
R5F563NWDGFB#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NWDGFB#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NWDGFB#V0?
For technical support, including R5F563NWDGFB#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NWDGFB#V0 requirements.
6.How does Aetrix verify that R5F563NWDGFB#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NWDGFB#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NWDGFB#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NWDGFB#V0?
All R5F563NWDGFB#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NWDGFB#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NWDGFB#V0 part is unused and in its original packaging.
Return procedure for R5F563NWDGFB#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563NWDGFB#V0 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
