Renesas R5F563NWHGFP#V0
- Part No.:
- R5F563NWHGFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F563NWHGFP#V0.pdf
- Description:
- 32BIT MCU RX63N
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F563NWHGFP#V0 from Renesas is a 100 MHz 32-bit RX63N Group microcontroller with integrated Ethernet MAC, single-precision IEEE-754 FPU, 165 DMIPS performance, 1 MB on-chip flash, 192 KB SRAM, and 32 KB data flash. It operates from a 2.7–3.6 V supply, supports -40 to +105°C (G version), and targets industrial networking and embedded control systems requiring real-time connectivity and cryptographic acceleration.
For engineers reviewing the R5F563NWHGFP#V0 datasheet, R5F563NWHGFP#V0 pinout, R5F563NWHGFP#V0 application, or R5F563NWHGFP#V0 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-A (176-pin LQFP), confirmed Ethernet/USB/CAN/ADC peripherals, and two validated alternative parts for design flexibility in temperature-critical industrial applications.
Technical Context
The R5F563NWHGFP#V0 implements the 32-bit RX CPU core with 5-stage CISC Harvard pipeline, supporting variable-length instructions and ultra-compact code density. It integrates a dedicated Ethernet controller (ETHERC) compliant with IEEE 802.3 at 10/100 Mbps, MII/RMII interface, and EDMAC DMA engine for descriptor-based packet handling.
Its memory subsystem includes no-wait-state 100 MHz flash (1 MB), 192 KB SRAM, and 32 KB reprogrammable data flash (100,000 cycles). The MCU features AES encryption via DEU (128/192/256-bit keys, ECB/CBC), 12-bit A/D converter (21 channels, 1 µs conversion @50 MHz PCLK), and dual 10-bit D/A outputs - all operating within its extended -40 to +105°C thermal envelope.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RX 32-bit CPU, 100 MHz max, 165 DMIPS - enables deterministic real-time execution of complex control and protocol stacks. |
| Flash Memory | 1 MB on-chip flash, 100 MHz no-wait access - sufficient for full TCP/IP stack + application firmware with fast boot and update capability. |
| SRAM | 192 KB on-chip SRAM, no-wait access - supports large Ethernet frame buffers, USB descriptors, and real-time task stacks without external RAM. |
| Ethernet Interface | IEEE 802.3-compliant MAC with MII/RMII, 10/100 Mbps full/half-duplex - enables direct PHY connection for industrial Ethernet nodes without external switch logic. |
| A/D Converter | 21-channel 12-bit S12AD, 1 µs conversion time @50 MHz PCLK - provides high-speed analog sensing for motor control, power monitoring, and sensor fusion. |
| Operating Temperature | -40 to +105°C (G version) - qualified for under-hood automotive, factory automation, and outdoor infrastructure deployments. |
| Cryptographic Engine | DEU with AES-128/192/256, ECB/CBC modes - accelerates secure boot, firmware authentication, and TLS handshake operations in resource-constrained edge devices. |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LQFP, 24 × 24 mm, 0.5 mm pitch, RoHS-compliant, surface-mount.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated 2.7–3.6 V core I/O rails with decoupling requirements per Renesas layout guidelines for noise immunity. |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal for precise system clock generation; internal PLL achieves 100 MHz ICLK. |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3 MDIO/MDC signals for PHY register configuration and status polling without CPU intervention. |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data bus (MII) | 16-bit parallel MII interface - requires matched trace lengths and controlled impedance for reliable 100 Mbps operation. |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 full-speed transceiver | Integrated USB PHY supports host/function/OTG; VBUS detection enables automatic mode switching and enumeration control. |
| AD[20:0] | Analog input channels | 21 dedicated pins for 12-bit S12AD - includes internal sample-and-hold and selectable reference (VREFH/VSS). |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet MAC + EDMAC | Hardware-accelerated packet transmission/reception with 2 KB TX/RX FIFOs reduces CPU load by >70% vs. software-only stack. |
| Floating-point unit (FPU) | Single-precision IEEE-754 compliance enables efficient math-intensive tasks like PID tuning, FFT-based signal analysis, and sensor calibration. |
| Temperature sensor | On-die ±1°C accuracy sensor feeds directly into 12-bit ADC - eliminates external thermistor BOM and calibration overhead. |
| Memory protection unit (MPU) | Configurable region-based access control prevents accidental or malicious overwrites of critical code/data sections during multitasking. |
| Real-time clock (RTC) | Battery-backed calendar/clock with alarm and periodic interrupts - maintains time across deep software standby modes for scheduled wake-up events. |
| IEBus interface | Integrated IEBus controller (ISO 9141-2 compatible) supports legacy automotive diagnostics and infotainment communication without external bridge ICs. |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering |
|---|---|
|
Use Scenario: Aggregating Modbus RTU/ASCII data from field sensors and bridging to cloud via Ethernet/WAN. IC Role / Device Role / Timing Role: Central protocol translator and real-time scheduler with hardware Ethernet MAC and deterministic interrupt latency. Use Value: 1 MB flash stores dual firmware images; 192 KB SRAM buffers multiple concurrent TCP connections; DEU secures OTA updates. |
Use Scenario: High-accuracy electricity meter with harmonic analysis, tamper detection, and remote firmware updates. IC Role / Device Role / Timing Role: Precision analog front-end controller with 21-channel 12-bit ADC, RTC for billing timestamps, and AES for encrypted data upload. Use Value: On-chip temperature sensor compensates ADC drift; 100 MHz core executes IEC 61850-compliant sampling algorithms in real time. |
| Automotive Body Control Module (BCM) | Factory Automation PLC I/O Node |
|
Use Scenario: Centralized lighting, door lock, and HVAC control in passenger vehicles with CAN/LIN/Ethernet backhaul. IC Role / Device Role / Timing Role: Multi-protocol hub with 3 CAN channels, LIN-capable SCId, and IEBus for legacy ECU integration. Use Value: G-version rating (-40 to +105°C) ensures reliability in engine bay proximity; unique ID enables VIN-linked security provisioning. |
Use Scenario: Distributed I/O module connecting analog/digital sensors and actuators to EtherCAT or PROFINET master controllers. IC Role / Device Role / Timing Role: Deterministic peripheral manager with MTU2/TPU timers for PWM motor control and PDC for vision sensor interfacing. Use Value: 176-pin LQFP provides 133 GPIOs with 5-V tolerance for industrial-level signal robustness; 4 low-power modes reduce standby consumption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NWDDFC | Same RX63N Group, identical 1 MB flash / 192 KB SRAM / 32 KB data flash, but D version (-40 to +85°C) and PLQP0176KB-A package. | Limited to commercial/industrial ambient environments; lacks extended temperature qualification for under-hood or outdoor enclosures. | Select when thermal margin is sufficient and cost sensitivity favors standard-grade silicon. |
| R5F563NWHDFC | Same G-version temperature range (-40 to +105°C), same 1 MB/192 KB/32 KB memory config, but uses PLQP0176KB-A package without #V0 suffix (standard tape-and-reel). | No functional difference; #V0 denotes specific Renesas packaging variant (e.g., moisture-sensitive level, reel size) - not electrical or thermal. | Choose for standard logistics compatibility where #V0-specific handling is unnecessary. |
Compared with R5F563NWHGFP#V0, R5F563NWDDFC trades extended temperature operation for lower cost in benign environments, while R5F563NWHDFC offers identical functionality without the #V0 packaging designation - enabling drop-in substitution where tape-and-reel format is unrestricted.
Availability
R5F563NWHGFP#V0 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, automotive body controllers, and factory automation I/O nodes requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for R5F563NWHGFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group is designed for high-performance, connectivity-rich embedded applications demanding integrated Ethernet, USB, CAN, and hardware security - targeting industrial control, building automation, and automotive subsystems.
FAQ
What is the maximum operating frequency and core architecture of the R5F563NWHGFP#V0?
The R5F563NWHGFP#V0 operates at a maximum frequency of 100 MHz using the 32-bit RX CPU core with a 5-stage CISC Harvard pipeline. It delivers 165 DMIPS performance and includes single-precision IEEE-754 floating-point support, making it suitable for computationally intensive real-time control tasks. The core also features memory protection unit (MPU) and JTAG/FINE debugging interfaces.
Does the R5F563NWHGFP#V0 include an Ethernet controller, and what standards does it support?
Yes, the R5F563NWHGFP#V0 integrates a full IEEE 802.3-compliant Ethernet MAC supporting both 10 Mbps and 100 Mbps operation in full- and half-duplex modes. It supports MII and RMII physical layer interfaces and includes flow control per IEEE 802.3x, Magic Packet™ wake-on-LAN detection, and a dedicated EDMAC DMA engine for descriptor-based packet processing - all confirmed in the RX63N Group datasheet R01DS0098EJ0180.
What are the memory resources available on the R5F563NWHGFP#V0?
The R5F563NWHGFP#V0 includes 1 MB of on-chip flash memory (100 MHz, no-wait access), 192 KB of on-chip SRAM (no-wait access), and 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles. These resources support robust firmware storage, real-time packet buffering, and non-volatile parameter retention - essential for industrial and automotive applications requiring field-upgradable code and persistent configuration.
What is the operating temperature range and package type for the R5F563NWHGFP#V0?
The R5F563NWHGFP#V0 is a G-version device rated for -40 to +105°C operation and housed in a PLQP0176KB-A package: a 176-pin LQFP with 24 × 24 mm footprint and 0.5 mm pitch. This package supports fine-pitch PCB assembly and meets industrial thermal and mechanical reliability requirements, including moisture sensitivity level (MSL) 3 compliance.
Which communication interfaces are integrated into the R5F563NWHGFP#V0?
The R5F563NWHGFP#V0 integrates Ethernet MAC (10/100 Mbps), USB 2.0 full-speed host/function/OTG (with 2 KB buffer), three CAN 2.0B modules (32 mailboxes each), four I²C interfaces (up to 1 Mbps), 13 SCI channels (supporting UART, SPI, I²C, LIN), three RSPI ports, one IEBus controller, and a parallel data capture unit (PDC). All are documented in the RX63N Group hardware manual R01DS0098EJ0180.
R5F563NWHGFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 14x12b; D/A 1x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NWHGFP#V0 FAQ
1.How can I place an order for R5F563NWHGFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NWHGFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NWHGFP#V0 reliable?
The price and inventory of R5F563NWHGFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NWHGFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NWHGFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NWHGFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NWHGFP#V0?
R5F563NWHGFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NWHGFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NWHGFP#V0?
For technical support, including R5F563NWHGFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NWHGFP#V0 requirements.
6.How does Aetrix verify that R5F563NWHGFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NWHGFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NWHGFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NWHGFP#V0?
All R5F563NWHGFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NWHGFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NWHGFP#V0 part is unused and in its original packaging.
Return procedure for R5F563NWHGFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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