Renesas R5F563NYDDFB#V0
- Part No.:
- R5F563NYDDFB#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F563NYDDFB#V0.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,279
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563NYDDFB#V0 from Renesas is a 100 MHz 32-bit RXv1 CPU-based microcontroller in the RX63N Group, featuring integrated Ethernet MAC (10/100 Mbps), full-speed USB 2.0 host/function/OTG, three CAN channels, 12-bit and 10-bit A/D converters (21 + 8 channels), dual 10-bit D/A outputs, hardware AES encryption (DEU), and 1 MB on-chip flash with 256 KB SRAM - designed for industrial networking gateways requiring deterministic real-time control and secure connectivity.
For engineers reviewing the R5F563NYDDFB#V0 datasheet, R5F563NYDDFB#V0 pinout, R5F563NYDDFB#V0 application, or R5F563NYDDFB#V0 equivalent, this MCU delivers verified Ethernet + USB + CAN coexistence, IEEE 802.3-compliant MII/RMII interface, IEC60730 safety support (CRC, self-diagnostic A/D, oscillation detection), and -40°C to +85°C operation in a 144-pin LQFP package.
Technical Context
The R5F563NYDDFB#V0 implements the RXv1 32-bit CISC Harvard architecture with 5-stage pipeline, single-cycle 32×32 multiplier, IEEE-754 single-precision FPU (165 DMIPS @ 100 MHz), and memory protection unit (MPU). It supports little-endian data and instruction layout with configurable endian mode per external bus area.
Its peripheral set includes a dedicated EDMAC for Ethernet (2 KB TX/RX FIFO), dual DMAC (4+2 channels), DTC, and clock domain separation: ICLK (up to 100 MHz), PCLK (up to 50 MHz), FCLK/BCLK (up to 50 MHz), enabling precise timing isolation between CPU, peripherals, flash, and external bus interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC with 5-stage pipeline, 165 DMIPS @ 100 MHz, IEEE-754 FPU, MPU support |
| Max Operating Frequency | 100 MHz system clock (ICLK), enabling deterministic real-time execution with sub-10 ns instruction timing |
| Memory | 1 MB on-chip flash (no wait states @ 100 MHz), 256 KB SRAM (no wait states), 32 KB data flash (100k write cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), USB 2.0 full-speed host/function/OTG (dual ports), 3× CAN (ISO 11898-1, 32 mailboxes each) |
| Analog Peripherals | 21-channel 12-bit A/D (1 µs conversion @ 50 MHz PCLK), 8-channel 10-bit A/D, 2× 10-bit D/A, on-die temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256 (ECB/CBC) via DEU, CRC calculator (3 polynomials), IEC60730-compliant self-test functions |
| Package & Temp | 144-pin LQFP (PLQP0144KA-A, 20 × 20 mm, 0.5 mm pitch), industrial grade (-40°C to +85°C) |
Pinout & Package
Package: PLQP0144KA-A - 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch, exposed thermal pad (non-electrical), RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | 2.7–3.6 V core/analog supply; 14 dedicated VCC/VSS pairs ensure low-noise power delivery across high-speed digital and analog domains |
| XTAL / EXTAL | Main crystal oscillator input/output | Supports 4–16 MHz external crystal; enables precise 100 MHz system clock via PLL with ±0.1% stability over temp |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC for PHY register access and link configuration without CPU overhead |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet data lanes | MII interface pins; support 10/100 Mbps full/half-duplex; require matched 50 Ω trace impedance for signal integrity |
| USB_DP / USB_DM | USB 2.0 differential data pair | Full-speed (12 Mbps) transceiver pins; internal pull-up resistor selectable for device enumeration; ESD rated to ±8 kV HBM |
| CANH / CANL | CAN bus differential signals | Three independent CAN physical layer interfaces; each supports dominant/recessive voltage levels per ISO 11898-2 |
| AD00–AD20 | 12-bit A/D input channels | 21 dedicated analog inputs with shared sample-and-hold; support simultaneous sampling of up to 4 channels via trigger synchronization |
| DA0 / DA1 | 10-bit D/A output channels | Two buffered voltage outputs (0 V to VREFH); usable for precision biasing, waveform generation, or sensor calibration feedback |
Key Features
| Feature | Design Value |
|---|---|
| Ethernet + USB + CAN concurrency | Dedicated EDMAC offloads Ethernet DMA; dual USB ports and triple CAN controllers operate independently without resource contention |
| IEC60730 Class B compliance support | Hardware CRC, oscillation-stop detection, A/D self-diagnostic, IWDT with dedicated LOCO clock - all implemented in silicon for certified safety firmware |
| Flexible clock domain partitioning | Independent ICLK/PCLK/FCLK/BCLK dividers allow optimized power/performance trade-offs: e.g., CPU at 100 MHz while peripherals run at 25 MHz |
| Secure firmware update capability | On-chip DEU enables authenticated AES decryption of encrypted firmware images stored in external SPI flash or received over Ethernet/USB |
| Real-time deterministic I/O | TPU2 (6-channel) + TPU (12-channel) + MTU2 timers provide synchronized PWM, capture, and phase-counting with <100 ns jitter for motor control and encoder interfacing |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet MS/TP traffic across factory floor devices into unified MQTT/HTTP uplink. IC Role / Device Role / Timing Role: Primary protocol translation engine with concurrent Ethernet MAC, USB CDC ACM, and three isolated CAN controllers managing fieldbus bridging. Use Value: Eliminates need for external PHY or bridge ICs; 1 MB flash stores multiple protocol stacks; hardware CRC ensures packet integrity at line rate. |
Use Scenario: Multi-tariff electricity meter with pulse counting, tamper detection, and secure remote firmware updates via cellular backhaul. IC Role / Device Role / Timing Role: System-on-chip controller handling metrology ADC sampling, RTC-based billing intervals, AES-encrypted OTA updates, and RS485/IEBus communication. Use Value: Integrated 12-bit A/D with temperature compensation, battery-backed RTC, and DEU meet IEC 62056 and UL 61000-4-5 surge immunity requirements. |
| Building Automation Controller | Medical Infusion Pump Controller |
Use Scenario: HVAC zone controller coordinating fan speed, valve position, and environmental sensing using BACnet/IP and KNX-over-IP. IC Role / Device Role / Timing Role: Real-time scheduler executing PID loops at 10 ms intervals while maintaining Ethernet stack latency < 500 µs for supervisory commands. Use Value: MTU2 and TPU timers deliver jitter-free PWM for EC motors; USB OTG allows field service diagnostics via standard PC tools. |
Use Scenario: Safety-critical infusion pump with flow rate monitoring, occlusion detection, and alarm escalation over hospital LAN. IC Role / Device Role / Timing Role: Dual-redundant watchdog (WDT + IWDT), temperature-sensor-monitored CPU thermal margin, and CRC-protected parameter storage. Use Value: IEC60730-certified self-tests (A/D, clock, memory) enable Class B compliance; 10-bit D/A drives precision current sources for motor control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563NJDDFB#V0 | Same 144-pin LQFP package, 1.5 MB flash, 256 KB SRAM - higher code density margin for complex protocol stacks | Better suited for future-proofing with larger firmware footprints (e.g., TLS stack + web server) | Select when >1 MB flash headroom is required for field-upgradable features without PCB change |
| R5F563NBCDFB#V0 | Same package, 1 MB flash, 128 KB SRAM - reduced RAM vs. R5F563NYDDFB#V0 (256 KB) | Lower cost for applications with minimal buffer requirements (e.g., simple serial-to-Ethernet bridges) | Choose when SRAM usage stays below 100 KB and BOM cost sensitivity outweighs flexibility |
Compared with R5F563NYDDFB#V0, R5F563NJDDFB#V0 offers 500 KB more flash for layered security or cloud connectivity stacks, while R5F563NBCDFB#V0 trades 128 KB SRAM for lower unit cost - both retain identical peripheral sets, pinout, and thermal profile.
Availability
R5F563NYDDFB#V0 is available at Aetrix Electronics and suitable for industrial networking gateways, smart energy metering hubs, building automation controllers, and medical infusion pump controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F563NYDDFB#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX63N Group targets industrial automation and networked embedded systems, integrating Ethernet, USB, CAN, and safety features into a single chip to reduce system complexity and certification effort.
FAQ
What is the maximum operating frequency and core architecture of the R5F563NYDDFB#V0?
The R5F563NYDDFB#V0 operates at a maximum frequency of 100 MHz using the RXv1 32-bit CISC Harvard architecture with 5-stage pipeline, delivering 165 DMIPS and including a single-precision IEEE-754 floating-point unit. Its instruction set supports ultra-compact code density and variable-length encoding, enabling efficient use of the 1 MB on-chip flash memory in the R5F563NYDDFB#V0.
Does the R5F563NYDDFB#V0 support Ethernet connectivity, and what interface standards does it implement?
Yes, the R5F563NYDDFB#V0 integrates a full IEEE 802.3-compliant Ethernet MAC supporting both 10 Mbps and 100 Mbps operation in full- and half-duplex modes. It implements MII (Media Independent Interface) and RMII (Reduced MII) standards, includes hardware support for Magic Packet™ wake-on-LAN, and features a dedicated EDMAC with 2 KB transmit and receive FIFOs to minimize CPU overhead during packet processing in the R5F563NYDDFB#V0.
What analog peripherals are integrated into the R5F563NYDDFB#V0, and what are their key performance metrics?
The R5F563NYDDFB#V0 integrates a 21-channel 12-bit A/D converter with 1 µs conversion time (at 50 MHz PCLK), an 8-channel 10-bit A/D converter, two 10-bit D/A outputs, and an on-die temperature sensor accurate to ±1°C. The 12-bit A/D includes a sample-and-hold circuit and supports software, timer-triggered, or external-event-started conversions - all confirmed in the R5F563NYDDFB#V0 datasheet Rev.1.80.
How does the R5F563NYDDFB#V0 support functional safety standards such as IEC60730?
The R5F563NYDDFB#V0 provides hardware-level IEC60730 Class B compliance features including oscillation-stop detection, hardware CRC calculation (with three selectable polynomials), independent watchdog timer (IWDT) with dedicated LOCO clock, self-diagnostic A/D functionality, and clock frequency measurement circuits. These capabilities are silicon-verified and documented in the R5F563NYDDFB#V0's safety manual to streamline certification for household and industrial appliances.
What is the package type and thermal specification for the R5F563NYDDFB#V0?
The R5F563NYDDFB#V0 is housed in a 144-pin LQFP package (PLQP0144KA-A), measuring 20 × 20 mm with 0.5 mm pitch and an exposed thermal pad. It is rated for industrial temperature operation from -40°C to +85°C, with validated thermal performance under continuous 100 MHz operation and full peripheral activation - as specified in the R5F563NYDDFB#V0 datasheet section "Operating Temperature".
R5F563NYDDFB#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Core Processor:
- RX
- Core Size:
- 32-Bit Single-Core
- Speed:
- 100MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, SCI, SPI, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x10b, 21x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563NYDDFB#V0 FAQ
1.How can I place an order for R5F563NYDDFB#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563NYDDFB#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563NYDDFB#V0 reliable?
The price and inventory of R5F563NYDDFB#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563NYDDFB#V0 is usually 5 days.
3.What payment methods are accepted for R5F563NYDDFB#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563NYDDFB#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563NYDDFB#V0?
R5F563NYDDFB#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563NYDDFB#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563NYDDFB#V0?
For technical support, including R5F563NYDDFB#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563NYDDFB#V0 requirements.
6.How does Aetrix verify that R5F563NYDDFB#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563NYDDFB#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563NYDDFB#V0 meets industry standards.
7.What is the process for return or replacement of R5F563NYDDFB#V0?
All R5F563NYDDFB#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563NYDDFB#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563NYDDFB#V0 part is unused and in its original packaging.
Return procedure for R5F563NYDDFB#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563NYDDFB#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

