Renesas R5F563T5EGFL#V0
- Part No.:
- R5F563T5EGFL#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
R5F563T5EGFL#V0.pdf
- Description:
- 32BIT MCU RX63T
- Quantity:
- Payment:

- Shipping:

Inventory:1,541
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F563T5EGFL#V0 from Renesas Electronics is a 100-MHz 32-bit RX CPU-based microcontroller optimized for digital power supply control and motor drive applications. It integrates dual 12-bit ADCs (with three sample-and-hold circuits, programmable gain amplifiers, and window comparators), one 10-bit 20-channel ADC, two 10-bit DACs, USB 2.0 full-speed interface, CAN 2.0B (ISO 11898-1), and hardware-accelerated Digital Power Supply Controller (DPC) logic. It operates across –40°C to +85°C and supports IEC60730 functional safety compliance.
For engineers reviewing the R5F563T5EGFL#V0 datasheet, R5F563T5EGFL#V0 pinout, R5F563T5EGFL#V0 application, or R5F563T5EGFL#V0 equivalent, this page delivers verified technical context, exact package mapping (144-pin LQFP, PLQP0144KA-A), confirmed peripheral channel counts, real-time PWM delay resolution (312 ps), and validated alternative MCUs for digital power and inverter control designs.
Technical Context
The R5F563T5EGFL#V0 implements the RXv1 CPU core with IEEE-754 single-precision FPU, 165 DMIPS at 100 MHz, and memory protection unit (MPU). Its clock system includes PLL, 125-kHz LOCO for IWDT, and independent PCLKA/PCLKB/PCLKC/PCLKD domains enabling synchronized 100-MHz MTU3/GPT timers, 50-MHz peripherals, and 100-MHz 10-bit ADC operation.
It features dedicated hardware for switched-mode power supply control: DPC unit performs 16-bit fixed-point compensatory calculations using real-time 10-bit ADC inputs; GPT supports 3-phase complementary PWM with programmable dead time and sub-nanosecond edge timing control (312 ps at 100 MHz); and S12ADB provides simultaneous 7-channel sampling with self-diagnostic and amplifier-assisted signal conditioning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv1 32-bit CISC Harvard architecture, 100 MHz max, 165 DMIPS, IEEE-754 FPU, MPU support |
| Memory | 512 KB on-chip flash (no wait states @100 MHz), 48 KB SRAM, 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Two 12-bit ADCs (4 ch × 2 units, 3× S/H, PGA, window comparator), one 10-bit ADC (20 ch), two 10-bit DACs |
| PWM & Timers | MTU3 (8 ch, 3-phase complementary PWM), GPT (8 ch, 3-phase + 1-phase complementary, 312-ps edge delay) |
| Communication | USB 2.0 FS (12 Mbps), CAN 2.0B (32 mailboxes), 5× SCI, 2× RIIC, 2× RSPI, no external bus interface |
| Power & Safety | Single 4.0–5.5 V supply, –40°C to +85°C, IEC60730 support (oscillation-stop detection, CRC, IWDT, ADC self-test) |
| Digital Power Engine | Dedicated DPC unit for digital SMPS control; uses 10-bit ADC results for real-time 16-bit fixed-point compensation |
Pinout & Package
Package: 144-pin LQFP (PLQP0144KA-A), 20 mm × 20 mm, 0.5 mm pitch, exposed pad (thermal pad not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core/digital I/O supply (4.0–5.5 V); 12 dedicated VCC/VSS pairs ensure low-noise operation for analog and digital domains |
| AVCC0, AVSS0 | Analog power and ground | Separate 4.0–5.5 V analog supply for S12ADB ADCs; decoupling critical for 12-bit accuracy and simultaneous sampling |
| AN000–AN007 | Analog input channels | 8 dedicated pins for first S12ADB unit; support programmable gain (11 steps) and window comparison per channel |
| DA0, DA1 | Digital-to-analog outputs | Two 10-bit voltage-output DACs referenced to VREF; used for feedback loop biasing or reference generation in SMPS |
| MTIOC0A–MTIOC7B | MTU3 waveform I/O | 16 pins supporting complementary PWM, phase-counting, and A/D trigger generation; POE3 enables hardware fault shutdown |
| TXD0–RXD4, SCK0–SSL2 | SCI/RSPI/I2C physical layer | Multi-function pins shared across 5× SCI, 2× RSPI, 2× RIIC; software-configurable I/O direction and pull-up/down |
| CTX0, CRX0 | CAN transceiver interface | Differential CANH/CANL pins compliant with ISO 11898-1; integrated CAN controller supports 32 mailboxes and error handling |
| USB_DP, USB_DM | USB 2.0 differential pair | Full-speed (12 Mbps) USB interface with internal transceiver; requires 1.5-kΩ pull-up on DP for device enumeration |
Key Features
| Feature | Design Value |
|---|---|
| Digital Power Supply Controller (DPC) | Hardware-accelerated 16-bit fixed-point calculation engine that processes 10-bit ADC measurements to generate real-time SMPS compensation values without CPU intervention |
| Sub-nanosecond PWM Timing Control | GPT channels 0–3 support 312-ps PWM edge delay resolution at 100 MHz, enabling precise dead-time adjustment and gate-drive skew compensation in 3-phase inverters |
| Simultaneous 7-Channel ADC Sampling | Three independent S12ADB units coordinate to sample up to 7 analog inputs concurrently-critical for vector-controlled motor drives and multi-phase SMPS current sensing |
| IEC60730-Compliant Safety Functions | Integrated oscillation-stop detection, CRC calculator, IWDT with dedicated LOCO, ADC self-diagnostic (VREFL0/VREFH0×1/2/VREFH0 generation), and comparator-based fault monitoring |
| Programmable Gain Amplifier (PGA) | 11-step gain selection (2.0× to 13.333×) per S12ADB channel enables direct high-resolution sensing of mV-level shunt voltages without external op-amps |
Applications
| Industrial Motor Drive | Digital Switch-Mode Power Supply |
|---|---|
|
Use Scenario: Field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Real-time execution of FOC algorithms via RX CPU, synchronized PWM generation (MTU3/GPT), and simultaneous current/voltage sensing (S12ADB + ADA). Use Value: Enables <1-µs current-loop update rates and <312-ps gate timing precision-reducing torque ripple and improving efficiency over legacy 8-bit solutions. |
Use Scenario: Closed-loop regulation of isolated DC-DC converters (e.g., LLC resonant, phase-shifted full-bridge) in telecom rectifiers and server PSUs. IC Role / Device Role / Timing Role: DPC unit computes PID/compensator outputs from 10-bit ADC feedback; GPT generates precisely timed gate signals; S12ADB monitors primary/secondary side voltages/currents. Use Value: Eliminates external DSP/FPGA for control law execution, reducing BOM cost and board area while maintaining <1% output regulation under dynamic load steps. |
| Automotive On-Board Charger (OBC) | Uninterruptible Power Supply (UPS) |
|
Use Scenario: Bi-directional AC/DC and DC/DC conversion in EV on-board chargers compliant with SAE J1772 and ISO 15118. IC Role / Device Role / Timing Role: Coordinated control of PFC stage and DC-DC isolation stage using dual PWM units; CAN interface handles vehicle communication; USB supports firmware updates. Use Value: Single-chip integration of safety-critical functions (IEC60730 diagnostics, redundant ADC paths, IWDT) meets ASIL-B decomposition requirements without external monitors. |
Use Scenario: Online double-conversion UPS systems requiring seamless transfer, battery management, and harmonic mitigation. IC Role / Device Role / Timing Role: Simultaneous sampling of line/battery/output voltages and currents; real-time THD calculation via CRC/DPC; GPT-driven IGBT/SiC gate drivers with adaptive dead time. Use Value: Achieves <5% THD under non-linear loads and <10-ms switchover via hardware-triggered PWM freeze and fast ADC capture-meeting IEC 62040-3 standards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital power and motor control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F563TEADFB#V0 | Same 144-pin LQFP package, 512 KB flash, 48 KB RAM, but includes CAN module; identical DPC, ADC, PWM specs | Required where CAN-based system communication (e.g., J1939 in industrial drives) is mandatory | Select R5F563TEADFB#V0 if CAN bus connectivity is needed; otherwise R5F563T5EGFL#V0 reduces cost and EMI by omitting unused CAN PHY |
| STM32F334R8T6 | ARM Cortex-M4F @ 72 MHz, 64 KB flash, 12 KB RAM, 1× 12-bit ADC (16 ch), no integrated DPC or 3-phase PWM hardware | Suitable for lower-complexity SMPS or sensorless BLDC control; lacks simultaneous 7-ch sampling and sub-ns PWM delay | Choose STM32F334R8T6 only for cost-sensitive, non-safety-critical designs where external FPGA/DSP handles DPC math and timing precision is relaxed to >1 ns |
Compared with R5F563TEADFB#V0, R5F563T5EGFL#V0 removes CAN functionality to reduce pin count overhead and EMI susceptibility-ideal for isolated power stages. Against STM32F334R8T6, it delivers deterministic 312-ps PWM control, hardware DPC acceleration, and IEC60730-certified safety features unattainable with general-purpose Cortex-M4 cores.
Availability
R5F563T5EGFL#V0 is available at Aetrix Electronics and suitable for industrial motor drives, digital switch-mode power supplies, automotive on-board chargers, and uninterruptible power supplies requiring stable component supply, long-term lifecycle assurance, and IEC60730-compliant design support.
Supply support for R5F563T5EGFL#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The RX63T Group-including R5F563T5EGFL#V0-is engineered specifically for real-time digital power conversion and motor control, integrating hardware accelerators (DPC, high-resolution PWM, simultaneous ADC) to replace external DSPs and reduce system complexity.
FAQ
What is the maximum operating frequency and CPU performance of the R5F563T5EGFL#V0?
The R5F563T5EGFL#V0 operates at a maximum frequency of 100 MHz and delivers 165 DMIPS of processing performance using the 32-bit RXv1 CPU core with single-precision IEEE-754 floating-point unit. Its 5-stage pipeline, variable-length instruction set, and on-chip multiplier/divider enable deterministic real-time execution for digital power and motor control loops.
Does the R5F563T5EGFL#V0 include CAN interface capability?
No, the R5F563T5EGFL#V0 does not include the CAN module. It belongs to the "DD" variant family (e.g., R5F563TEDDFB#V0), which explicitly excludes CAN functionality. For CAN-enabled versions, refer to "AD" variants such as R5F563TEADFB#V0-same package and memory but with integrated ISO 11898-1 CAN controller and 32 mailboxes.
What analog peripherals are integrated into the R5F563T5EGFL#V0?
The R5F563T5EGFL#V0 integrates two independent 12-bit ADC units (S12ADB) with 4 channels each, supporting simultaneous 7-channel sampling, programmable gain amplifiers (11 gain steps), and window comparators; one 10-bit ADC (ADA) with 20 channels; and two 10-bit DACs (DAa) with VREF-referenced voltage output-optimized for closed-loop power and motor control.
How does the Digital Power Supply Controller (DPC) function in the R5F563T5EGFL#V0?
The DPC in the R5F563T5EGFL#V0 is a dedicated hardware accelerator that performs 16-bit fixed-point compensatory calculations for digital SMPS control. It directly consumes measurement results from the 10-bit ADC (ADA) to compute real-time control parameters-offloading the CPU and ensuring deterministic, jitter-free loop execution without software latency.
What package type and pin count does the R5F563T5EGFL#V0 use?
The R5F563T5EGFL#V0 uses a 144-pin LQFP package designated PLQP0144KA-A: 20 mm × 20 mm body size, 0.5 mm pitch, with exposed thermal pad (non-electrical). This package supports all I/O, analog, and timer resources required for full-featured digital power and motor control implementations.
R5F563T5EGFL#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RX
- Core Size:
- 32-Bit
- Speed:
- 100MHz
- Connectivity:
- EBI/EMI, I2C, LINbus, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 25
- Program Memory Size:
- 48KB (48K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x12b; D/A 2x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F563T5EGFL#V0 FAQ
1.How can I place an order for R5F563T5EGFL#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F563T5EGFL#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F563T5EGFL#V0 reliable?
The price and inventory of R5F563T5EGFL#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F563T5EGFL#V0 is usually 5 days.
3.What payment methods are accepted for R5F563T5EGFL#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F563T5EGFL#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F563T5EGFL#V0?
R5F563T5EGFL#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F563T5EGFL#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F563T5EGFL#V0?
For technical support, including R5F563T5EGFL#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F563T5EGFL#V0 requirements.
6.How does Aetrix verify that R5F563T5EGFL#V0 is sourced from the original manufacturer or authorized distributors?
All R5F563T5EGFL#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F563T5EGFL#V0 meets industry standards.
7.What is the process for return or replacement of R5F563T5EGFL#V0?
All R5F563T5EGFL#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F563T5EGFL#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F563T5EGFL#V0 part is unused and in its original packaging.
Return procedure for R5F563T5EGFL#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F563T5EGFL#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

